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120 lines
3.6 KiB
Diff
120 lines
3.6 KiB
Diff
From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Tue, 7 Dec 2021 11:49:21 +0100
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Subject: [PATCH] PCI: mt7621: Move MIPS setup to pcibios_root_bridge_prepare()
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On the MIPS ralink mt7621 platform, we need to set up I/O coherency units
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based on the host bridge apertures.
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To remove this arch dependency from the driver itself, move the coherency
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setup from the driver to pcibios_root_bridge_prepare().
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[bhelgaas: squash add/remove into one patch, commit log]
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Link: https://lore.kernel.org/r/20211207104924.21327-3-sergio.paracuellos@gmail.com
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Link: https://lore.kernel.org/r/20211207104924.21327-4-sergio.paracuellos@gmail.com
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Reviewed-by: Guenter Roeck <linux@roeck-us.net> # arch/mips
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Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> # arch/mips
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---
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--- a/arch/mips/ralink/mt7621.c
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+++ b/arch/mips/ralink/mt7621.c
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@@ -10,6 +10,8 @@
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#include <linux/slab.h>
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#include <linux/sys_soc.h>
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#include <linux/memblock.h>
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+#include <linux/pci.h>
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+#include <linux/bug.h>
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#include <asm/bootinfo.h>
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#include <asm/mipsregs.h>
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@@ -24,6 +26,35 @@
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static u32 detect_magic __initdata;
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+int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
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+{
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+ struct resource_entry *entry;
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+ resource_size_t mask;
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+
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+ entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
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+ if (!entry) {
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+ pr_err("Cannot get memory resource\n");
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+ return -EINVAL;
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+ }
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+
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+ if (mips_cps_numiocu(0)) {
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+ /*
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+ * Hardware doesn't accept mask values with 1s after
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+ * 0s (e.g. 0xffef), so warn if that's happen
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+ */
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+ mask = ~(entry->res->end - entry->res->start) & CM_GCR_REGn_MASK_ADDRMASK;
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+ WARN_ON(mask && BIT(ffz(~mask)) - 1 != ~mask);
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+
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+ write_gcr_reg1_base(entry->res->start);
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+ write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
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+ pr_info("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
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+ (unsigned long long)read_gcr_reg1_base(),
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+ (unsigned long long)read_gcr_reg1_mask());
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+ }
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+
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+ return 0;
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+}
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+
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phys_addr_t mips_cpc_default_phys_base(void)
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{
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panic("Cannot detect cpc address");
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--- a/drivers/pci/controller/pcie-mt7621.c
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+++ b/drivers/pci/controller/pcie-mt7621.c
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@@ -208,37 +208,6 @@ static inline void mt7621_control_deasse
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reset_control_assert(port->pcie_rst);
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}
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-static int setup_cm_memory_region(struct pci_host_bridge *host)
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-{
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- struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
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- struct device *dev = pcie->dev;
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- struct resource_entry *entry;
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- resource_size_t mask;
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-
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- entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
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- if (!entry) {
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- dev_err(dev, "cannot get memory resource\n");
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- return -EINVAL;
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- }
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-
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- if (mips_cps_numiocu(0)) {
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- /*
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- * FIXME: hardware doesn't accept mask values with 1s after
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- * 0s (e.g. 0xffef), so it would be great to warn if that's
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- * about to happen
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- */
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- mask = ~(entry->res->end - entry->res->start);
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-
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- write_gcr_reg1_base(entry->res->start);
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- write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
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- dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
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- (unsigned long long)read_gcr_reg1_base(),
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- (unsigned long long)read_gcr_reg1_mask());
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- }
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-
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- return 0;
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-}
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-
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static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
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struct device_node *node,
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int slot)
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@@ -557,12 +526,6 @@ static int mt7621_pcie_probe(struct plat
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goto remove_resets;
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}
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- err = setup_cm_memory_region(bridge);
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- if (err) {
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- dev_err(dev, "error setting up iocu mem regions\n");
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- goto remove_resets;
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- }
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-
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return mt7621_pcie_register_host(bridge);
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remove_resets:
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