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b7e9445d6d
Import pending patches adding support for MT7988 and provide builds for the reference board for all possible boot media. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
50 lines
1.4 KiB
Diff
50 lines
1.4 KiB
Diff
From b4a308dd31a7c6754be230849a5e430052268b9c Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 19 Jul 2023 17:16:33 +0800
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Subject: [PATCH 11/29] reset: mediatek: add reset definition for MediaTek
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MT7988 SoC
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This patch adds reset bits for MediaTek MT7988
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Signed-off-by: Sam Shih <sam.shih@mediatek.com>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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include/dt-bindings/reset/mt7988-reset.h | 31 ++++++++++++++++++++++++
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1 file changed, 31 insertions(+)
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create mode 100644 include/dt-bindings/reset/mt7988-reset.h
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--- /dev/null
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+++ b/include/dt-bindings/reset/mt7988-reset.h
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@@ -0,0 +1,31 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+/*
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+ * Copyright (C) 2023 MediaTek Inc.
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+ */
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+
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+#ifndef _DT_BINDINGS_MTK_RESET_H_
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+#define _DT_BINDINGS_MTK_RESET_H_
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+
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+/* ETHDMA Subsystem resets */
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+#define ETHDMA_FE_RST 6
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+#define ETHDMA_PMTR_RST 8
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+#define ETHDMA_GMAC_RST 23
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+#define ETHDMA_WDMA0_RST 24
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+#define ETHDMA_WDMA1_RST 25
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+#define ETHDMA_WDMA2_RST 26
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+#define ETHDMA_PPE0_RST 29
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+#define ETHDMA_PPE1_RST 30
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+#define ETHDMA_PPE2_RST 31
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+
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+/* ETHWARP Subsystem resets */
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+#define ETHWARP_GSW_RST 9
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+#define ETHWARP_EIP197_RST 10
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+#define ETHWARP_WOCPU0_RST 32
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+#define ETHWARP_WOCPU1_RST 33
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+#define ETHWARP_WOCPU2_RST 34
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+#define ETHWARP_WOX_NET_MUX_RST 35
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+#define ETHWARP_WED0_RST 36
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+#define ETHWARP_WED1_RST 37
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+#define ETHWARP_WED2_RST 38
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+
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+#endif /* _DT_BINDINGS_MTK_RESET_H_ */
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