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openwrt/target/linux/airoha/dts/an7581.dtsi
Christian Marangi d7dc5b1b4d
airoha: rename subtarget from en7581 to an7581 
The Airoha EN7581 got renamed to AN7581 due to move from Econet to
Airoha.

To save on compatibility, use both compatible for the device.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
2024-10-23 12:32:03 +02:00

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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/en7523-clk.h>
#include <dt-bindings/reset/airoha,en7581-reset.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
npu-binary@84000000 {
no-map;
reg = <0x0 0x84000000 0x0 0xa00000>;
};
npu-flag@84b0000 {
no-map;
reg = <0x0 0x84b00000 0x0 0x100000>;
};
npu-pkt@85000000 {
no-map;
reg = <0x0 0x85000000 0x0 0x1a00000>;
};
npu-phyaddr@86b00000 {
no-map;
reg = <0x0 0x86b00000 0x0 0x100000>;
};
npu-rxdesc@86d00000 {
no-map;
reg = <0x0 0x86d00000 0x0 0x100000>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
clock-frequency = <80000000>;
next-level-cache = <&l2>;
#cooling-cells = <2>;
};
l2: l2-cache {
compatible = "cache";
cache-size = <0x80000>;
cache-line-size = <64>;
cache-level = <2>;
cache-unified;
};
};
cpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-shared;
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
};
opp-550000000 {
opp-hz = /bits/ 64 <550000000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
};
opp-650000000 {
opp-hz = /bits/ 64 <650000000>;
};
opp-7000000000 {
opp-hz = /bits/ 64 <700000000>;
};
opp-7500000000 {
opp-hz = /bits/ 64 <750000000>;
};
opp-8000000000 {
opp-hz = /bits/ 64 <800000000>;
};
opp-8500000000 {
opp-hz = /bits/ 64 <850000000>;
};
opp-9000000000 {
opp-hz = /bits/ 64 <900000000>;
};
opp-9500000000 {
opp-hz = /bits/ 64 <950000000>;
};
opp-10000000000 {
opp-hz = /bits/ 64 <1000000000>;
};
opp-10500000000 {
opp-hz = /bits/ 64 <1050000000>;
};
opp-11000000000 {
opp-hz = /bits/ 64 <1100000000>;
};
opp-11500000000 {
opp-hz = /bits/ 64 <1150000000>;
};
opp-12000000000 {
opp-hz = /bits/ 64 <1200000000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&thermal 0>;
trips {
cpu_hot: cpu-hot {
temperature = <95000>;
hysteresis = <1000>;
type = "hot";
};
cpu-critical {
temperature = <110000>;
hysteresis = <1000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_hot>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@9000000 {
compatible = "arm,gic-v3";
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x09000000 0x0 0x20000>,
<0x0 0x09080000 0x0 0x80000>,
<0x0 0x09400000 0x0 0x2000>,
<0x0 0x09500000 0x0 0x2000>,
<0x0 0x09600000 0x0 0x20000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
uart1: serial@1fbf0000 {
compatible = "ns16550";
reg = <0x0 0x1fbf0000 0x0 0x30>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <1843200>;
};
watchdog@1fbf0100 {
compatible = "airoha,en7581-wdt";
reg = <0x0 0x1fbf0100 0x0 0x38>;
clocks = <&scuclk EN7523_CLK_BUS>;
clock-names = "bus";
};
uart2: serial@1fbf0300 {
compatible = "airoha,en7523-uart";
reg = <0x0 0x1fbf0300 0x0 0x30>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <7372800>;
status = "disabled";
};
hsuart3: serial@1fbe1000 {
compatible = "airoha,en7523-uart";
reg = <0x0 0x1fbe1000 0x0 0x40>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <7372800>;
status = "disabled";
};
uart4: serial@1fbf0600 {
compatible = "airoha,en7523-uart";
reg = <0x0 0x1fbf0600 0x0 0x30>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <7372800>;
status = "disabled";
};
uart5: serial@1fbf0700 {
compatible = "airoha,en7523-uart";
reg = <0x0 0x1fbf0700 0x0 0x30>;
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <7372800>;
status = "disabled";
};
chip_scu: syscon@1fa20000 {
compatible = "airoha,en7581-chip-scu", "syscon";
reg = <0x0 0x1fa20000 0x0 0x388>;
};
syscon@1fbe3400 {
compatible = "airoha,en7581-pbus-csr", "syscon";
reg = <0x0 0x1fbe3400 0x0 0xff>;
};
scuclk: clock-controller@1fa20000 {
compatible = "airoha,en7581-scu";
reg = <0x0 0x1fb00000 0x0 0x970>;
#clock-cells = <1>;
#reset-cells = <1>;
};
rng@1faa1000 {
compatible = "airoha,en7581-trng";
reg = <0x0 0x1faa1000 0x0 0xc04>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
};
crypto@1e004000 {
compatible = "inside-secure,safexcel-eip93ies";
reg = <0x0 0x1fb70000 0x0 0x1000>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
};
thermal: thermal-sensor@1efbd800 {
compatible = "airoha,en7581-thermal";
reg = <0x0 0x1efbd000 0x0 0xd5c>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
airoha,chip-scu = <&chip_scu>;
#thermal-sensor-cells = <0>;
};
system-controller@1fbf0200 {
compatible = "syscon", "simple-mfd";
reg = <0x0 0x1fbf0200 0x0 0xc0>;
en7581_pinctrl: pinctrl {
compatible = "airoha,en7581-pinctrl";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
en7581_pwm: pwm {
compatible = "airoha,en7581-pwm";
#pwm-cells = <3>;
};
};
i2cclock: i2cclock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* 20 MHz */
clock-frequency = <20000000>;
};
i2c0: i2c0@1fbf8000 {
compatible = "mediatek,mt7621-i2c";
reg = <0x0 0x1fbf8000 0x0 0x100>;
clocks = <&i2cclock>;
/* 100 kHz */
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disable";
};
i2c1: i2c1@1fbf8100 {
compatible = "mediatek,mt7621-i2c";
reg = <0x0 0x1fbf8100 0x0 0x100>;
clocks = <&i2cclock>;
/* 100 kHz */
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disable";
};
snfi: spi@1fa10000 {
compatible = "airoha,en7581-snand";
reg = <0x0 0x1fa10000 0x0 0x140>,
<0x0 0x1fa11000 0x0 0x160>;
clocks = <&scuclk EN7523_CLK_SPI>;
clock-names = "spi";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
spi_nand: nand@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <2>;
airoha,bmt;
};
};
mmc0: mmc@1fa0e000 {
compatible = "mediatek,mt7622-mmc";
reg = <0x0 0x1fa0e000 0x0 0x1000>,
<0x0 0x1fa0c000 0x0 0x60>;
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <4>;
max-frequency = <52000000>;
disable-wp;
cap-mmc-highspeed;
non-removable;
status = "disabled";
};
pciephy: phy@1fa5a000 {
compatible = "airoha,en7581-pcie-phy";
reg = <0x0 0x1fa5a000 0x0 0xfff>,
<0x0 0x1fa5b000 0x0 0xfff>,
<0x0 0x1fa5c000 0x0 0xfff>,
<0x0 0x1fc10044 0x0 0x4>,
<0x0 0x1fc30044 0x0 0x4>,
<0x0 0x1fc15030 0x0 0x104>;
reg-names = "csr-2l", "pma0", "pma1",
"p0-xr-dtime", "p1-xr-dtime",
"rx-aeq";
#phy-cells = <0>;
};
pcie0: pcie@1fc00000 {
compatible = "airoha,en7581-pcie";
device_type = "pci";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x1fc00000 0x0 0x1670>;
reg-names = "pcie-mac";
clocks = <&scuclk EN7523_CLK_PCIE>;
clock-names = "sys-ck";
phys = <&pciephy>;
phy-names = "pcie-phy";
ranges = <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000>;
resets = <&scuclk EN7581_PCIE0_RST>,
<&scuclk EN7581_PCIE1_RST>,
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc0 0>,
<0 0 0 2 &pcie_intc0 1>,
<0 0 0 3 &pcie_intc0 2>,
<0 0 0 4 &pcie_intc0 3>;
status = "disabled";
pcie_intc0: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
pcie1: pcie@1fc20000 {
compatible = "airoha,en7581-pcie";
device_type = "pci";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
reg = <0x0 0x1fc20000 0x0 0x1670>;
reg-names = "pcie-mac";
clocks = <&scuclk EN7523_CLK_PCIE>;
clock-names = "sys-ck";
phys = <&pciephy>;
phy-names = "pcie-phy";
ranges = <0x02000000 0 0x24000000 0x0 0x24000000 0 0x4000000>;
resets = <&scuclk EN7581_PCIE0_RST>,
<&scuclk EN7581_PCIE1_RST>,
<&scuclk EN7581_PCIE2_RST>;
reset-names = "phy-lane0", "phy-lane1", "phy-lane2";
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
bus-range = <0x00 0xff>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc1 0>,
<0 0 0 2 &pcie_intc1 1>,
<0 0 0 3 &pcie_intc1 2>,
<0 0 0 4 &pcie_intc1 3>;
status = "disabled";
pcie_intc1: interrupt-controller {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
};
eth: ethernet@1fb50000 {
compatible = "airoha,en7581-eth";
reg = <0 0x1fb50000 0 0x2600>,
<0 0x1fb54000 0 0x2000>,
<0 0x1fb56000 0 0x2000>;
reg-names = "fe", "qdma0", "qdma1";
resets = <&scuclk EN7581_FE_RST>,
<&scuclk EN7581_FE_PDMA_RST>,
<&scuclk EN7581_FE_QDMA_RST>,
<&scuclk EN7581_XSI_MAC_RST>,
<&scuclk EN7581_DUAL_HSI0_MAC_RST>,
<&scuclk EN7581_DUAL_HSI1_MAC_RST>,
<&scuclk EN7581_HSI_MAC_RST>,
<&scuclk EN7581_XFP_MAC_RST>;
reset-names = "fe", "pdma", "qdma", "xsi-mac",
"hsi0-mac", "hsi1-mac", "hsi-mac",
"xfp-mac";
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
gdm1: ethernet@1 {
compatible = "airoha,eth-mac";
reg = <1>;
phy-mode = "internal";
status = "disabled";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
switch: switch@1fb58000 {
compatible = "airoha,en7581-switch";
reg = <0 0x1fb58000 0 0x8000>;
resets = <&scuclk EN7581_GSW_RST>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
gsw_port1: port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&gsw_phy1>;
};
gsw_port2: port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&gsw_phy2>;
};
gsw_port3: port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&gsw_phy3>;
};
gsw_port4: port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&gsw_phy4>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gdm1>;
phy-mode = "internal";
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <9>;
phy-mode = "internal";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy1_led0: gsw-phy1-led0@0 {
reg = <0>;
function = "phy1_led0";
status = "disabled";
};
gsw_phy1_led1: gsw-phy1-led1@1 {
reg = <1>;
function = "phy1_led1";
status = "disabled";
};
};
};
gsw_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <10>;
phy-mode = "internal";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy2_led0: gsw-phy2-led0@0 {
reg = <0>;
function = "phy2_led0";
status = "disabled";
};
gsw_phy2_led1: gsw-phy2-led1@1 {
reg = <1>;
function = "phy1_led1";
status = "disabled";
};
};
};
gsw_phy3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <11>;
phy-mode = "internal";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy3_led0: gsw-phy3-led0@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
gsw_phy3_led1: gsw-phy3-led1@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
};
};
gsw_phy4: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <12>;
phy-mode = "internal";
leds {
#address-cells = <1>;
#size-cells = <0>;
gsw_phy4_led0: gsw-phy4-led0@0 {
reg = <0>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
gsw_phy4_led1: gsw-phy4-led1@1 {
reg = <1>;
function = LED_FUNCTION_LAN;
status = "disabled";
};
};
};
};
};
};
};
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