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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
89 lines
2.2 KiB
Diff
89 lines
2.2 KiB
Diff
From 7492ebbdd926da258f9abea5c41a9f8c4ec48631 Mon Sep 17 00:00:00 2001
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From: Changhuang Liang <changhuang.liang@starfivetech.com>
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Date: Mon, 29 May 2023 05:15:01 -0700
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Subject: [PATCH 074/122] dt-bindings: phy: Add starfive,jh7110-dphy-rx
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StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
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a M31 IP. Add a binding for it.
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Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
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---
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.../bindings/phy/starfive,jh7110-dphy-rx.yaml | 71 +++++++++++++++++++
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1 file changed, 71 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-dphy-rx.yaml
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@@ -0,0 +1,71 @@
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive SoC MIPI D-PHY Rx Controller
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+
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+maintainers:
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+ - Jack Zhu <jack.zhu@starfivetech.com>
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+ - Changhuang Liang <changhuang.liang@starfivetech.com>
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+
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+description:
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+ The StarFive SoC uses the MIPI CSI D-PHY based on M31 IP to transfer
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+ CSI camera data.
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-dphy-rx
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ items:
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+ - description: config clock
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+ - description: reference clock
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+ - description: escape mode transmit clock
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+
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+ clock-names:
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+ items:
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+ - const: cfg
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+ - const: ref
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+ - const: tx
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+
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+ resets:
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+ items:
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+ - description: DPHY_HW reset
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+ - description: DPHY_B09_ALWAYS_ON reset
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+
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+ power-domains:
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+ maxItems: 1
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+
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+ "#phy-cells":
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+ const: 0
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+ - resets
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+ - power-domains
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+ - "#phy-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ phy@19820000 {
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+ compatible = "starfive,jh7110-dphy-rx";
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+ reg = <0x19820000 0x10000>;
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+ clocks = <&ispcrg 3>,
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+ <&ispcrg 4>,
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+ <&ispcrg 5>;
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+ clock-names = "cfg", "ref", "tx";
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+ resets = <&ispcrg 2>,
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+ <&ispcrg 3>;
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+ power-domains = <&dphy_pwrc 1>;
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+ #phy-cells = <0>;
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+ };
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