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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
81 lines
2.4 KiB
Diff
81 lines
2.4 KiB
Diff
From 07f62b08668c0295b1c6342f9708b7e36093ff59 Mon Sep 17 00:00:00 2001
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From: Xingyu Wu <xingyu.wu@starfivetech.com>
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Date: Tue, 21 Feb 2023 17:13:48 +0800
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Subject: [PATCH 031/122] dt-bindings: clock: Add StarFive JH7110 PLL clock
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generator
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Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
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---
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.../bindings/clock/starfive,jh7110-pll.yaml | 46 +++++++++++++++++++
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.../dt-bindings/clock/starfive,jh7110-crg.h | 6 +++
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2 files changed, 52 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
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@@ -0,0 +1,46 @@
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 PLL Clock Generator
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+
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+description:
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+ This PLL are high speed, low jitter frequency synthesizers in JH7110.
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+ Each PLL clocks work in integer mode or fraction mode by some dividers,
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+ and the configuration registers and dividers are set in several syscon
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+ registers. So pll node should be a child of SYS-SYSCON node.
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+ The formula for calculating frequency is that,
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+ Fvco = Fref * (NI + NF) / M / Q1
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+
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+maintainers:
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+ - Xingyu Wu <xingyu.wu@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-pll
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+
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+ clocks:
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+ maxItems: 1
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+ description: Main Oscillator (24 MHz)
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+
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+ '#clock-cells':
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+ const: 1
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+ description:
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+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
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+
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+required:
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+ - compatible
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+ - clocks
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+ - '#clock-cells'
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ pll-clock-controller {
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+ compatible = "starfive,jh7110-pll";
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+ clocks = <&osc>;
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+ #clock-cells = <1>;
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+ };
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--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
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+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
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@@ -6,6 +6,12 @@
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#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
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#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
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+/* PLL clocks */
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+#define JH7110_CLK_PLL0_OUT 0
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+#define JH7110_CLK_PLL1_OUT 1
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+#define JH7110_CLK_PLL2_OUT 2
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+#define JH7110_PLLCLK_END 3
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+
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/* SYSCRG clocks */
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#define JH7110_SYSCLK_CPU_ROOT 0
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#define JH7110_SYSCLK_CPU_CORE 1
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