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This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
31 lines
1.2 KiB
Diff
31 lines
1.2 KiB
Diff
From d03341ef7acb64803ade6b173d24f49ffa6149a3 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Tue, 2 Aug 2022 00:29:32 -0500
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Subject: [PATCH 019/117] dt-bindings: nvmem: Allow bit offsets greater than a
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byte
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Some NVMEM devices contain cells which do not start at a multiple of the
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device's stride. However, the "reg" property of a cell must be aligned
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to its provider device's stride.
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These cells can be represented in the DT using the "bits" property if
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that property allows offsets up to the full stride. 63 is chosen
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assuming that NVMEM devices will not have strides larger than 8 bytes.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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Documentation/devicetree/bindings/nvmem/nvmem.yaml | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml
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+++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
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@@ -53,7 +53,7 @@ patternProperties:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- minimum: 0
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- maximum: 7
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+ maximum: 63
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description:
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Offset in bit within the address range specified by reg.
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- minimum: 1
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