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a497e47762
The patch was wrongly removed by a kernel version bump to 4.9.105 in
the believe that it was merged upstream thow it wasn't. This lead to
unrecoverable link losses on devices which use those PHYs such as
many ubnt single-port CPEs.
Fixes: 7dca1bae82 (kernel: bump to 4.9.105)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
143 lines
3.9 KiB
Diff
143 lines
3.9 KiB
Diff
From: Gabor Juhos <juhosg@openwrt.org>
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Subject: net: phy: allow to configure AR803x PHYs via platform data
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Add a patch for the at803x phy driver, in order to be able
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to configure some register settings via platform data.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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---
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drivers/net/phy/at803x.c | 56 ++++++++++++++++++++++++++++++++
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include/linux/platform_data/phy-at803x.h | 11 +++++++
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2 files changed, 67 insertions(+)
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create mode 100644 include/linux/platform_data/phy-at803x.h
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--- a/drivers/net/phy/at803x.c
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+++ b/drivers/net/phy/at803x.c
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@@ -12,12 +12,14 @@
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*/
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#include <linux/phy.h>
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+#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/of_gpio.h>
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#include <linux/gpio/consumer.h>
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+#include <linux/platform_data/phy-at803x.h>
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#define AT803X_INTR_ENABLE 0x12
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#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
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@@ -45,6 +47,11 @@
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#define AT803X_REG_CHIP_CONFIG 0x1f
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#define AT803X_BT_BX_REG_SEL 0x8000
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+#define AT803X_PCS_SMART_EEE_CTRL3 0x805D
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+#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_MASK 0x3
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+#define AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT 12
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+#define AT803X_SMART_EEE_CTRL3_LPI_EN BIT(8)
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+
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#define AT803X_DEBUG_ADDR 0x1D
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#define AT803X_DEBUG_DATA 0x1E
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@@ -72,6 +79,7 @@ MODULE_LICENSE("GPL");
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struct at803x_priv {
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bool phy_reset:1;
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struct gpio_desc *gpiod_reset;
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+ int prev_speed;
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};
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struct at803x_context {
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@@ -276,8 +284,16 @@ does_not_require_reset_workaround:
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return 0;
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}
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+static void at803x_disable_smarteee(struct phy_device *phydev)
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+{
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, AT803X_PCS_SMART_EEE_CTRL3,
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+ 1 << AT803X_SMART_EEE_CTRL3_LPI_TX_DELAY_SEL_SHIFT);
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+ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0);
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+}
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+
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static int at803x_config_init(struct phy_device *phydev)
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{
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+ struct at803x_platform_data *pdata;
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int ret;
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ret = genphy_config_init(phydev);
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@@ -298,6 +314,26 @@ static int at803x_config_init(struct phy
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return ret;
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}
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+ pdata = dev_get_platdata(&phydev->mdio.dev);
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+ if (pdata) {
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+ if (pdata->disable_smarteee)
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+ at803x_disable_smarteee(phydev);
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+
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+ if (pdata->enable_rgmii_rx_delay)
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+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
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+ AT803X_DEBUG_RX_CLK_DLY_EN);
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+ else
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+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
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+ AT803X_DEBUG_RX_CLK_DLY_EN, 0);
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+
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+ if (pdata->enable_rgmii_tx_delay)
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+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
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+ AT803X_DEBUG_TX_CLK_DLY_EN);
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+ else
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+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
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+ AT803X_DEBUG_TX_CLK_DLY_EN, 0);
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+ }
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+
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return 0;
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}
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@@ -335,6 +371,8 @@ static int at803x_config_intr(struct phy
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static void at803x_link_change_notify(struct phy_device *phydev)
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{
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struct at803x_priv *priv = phydev->priv;
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+ struct at803x_platform_data *pdata;
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+ pdata = dev_get_platdata(&phydev->mdio.dev);
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/*
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* Conduct a hardware reset for AT8030/2 every time a link loss is
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@@ -363,6 +401,24 @@ static void at803x_link_change_notify(st
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} else {
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priv->phy_reset = false;
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}
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+ if (pdata && pdata->fixup_rgmii_tx_delay &&
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+ phydev->speed != priv->prev_speed) {
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+ switch (phydev->speed) {
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+ case SPEED_10:
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+ case SPEED_100:
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+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
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+ AT803X_DEBUG_TX_CLK_DLY_EN);
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+ break;
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+ case SPEED_1000:
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+ at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
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+ AT803X_DEBUG_TX_CLK_DLY_EN, 0);
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ priv->prev_speed = phydev->speed;
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+ }
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}
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static int at803x_aneg_done(struct phy_device *phydev)
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--- /dev/null
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+++ b/include/linux/platform_data/phy-at803x.h
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@@ -0,0 +1,11 @@
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+#ifndef _PHY_AT803X_PDATA_H
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+#define _PHY_AT803X_PDATA_H
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+
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+struct at803x_platform_data {
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+ int disable_smarteee:1;
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+ int enable_rgmii_tx_delay:1;
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+ int enable_rgmii_rx_delay:1;
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+ int fixup_rgmii_tx_delay:1;
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+};
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+
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+#endif /* _PHY_AT803X_PDATA_H */
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