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400 lines
14 KiB
C
400 lines
14 KiB
C
/******************************************************************************
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**
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** FILE NAME : ifxmips_pcie_msi.c
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** PROJECT : IFX UEIP for VRX200
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** MODULES : PCI MSI sub module
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**
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** DATE : 02 Mar 2009
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** AUTHOR : Lei Chuanhua
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** DESCRIPTION : PCIe MSI Driver
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** COPYRIGHT : Copyright (c) 2009
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** Infineon Technologies AG
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** Am Campeon 1-12, 85579 Neubiberg, Germany
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**
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** This program is free software; you can redistribute it and/or modify
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** it under the terms of the GNU General Public License as published by
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** the Free Software Foundation; either version 2 of the License, or
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** (at your option) any later version.
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** HISTORY
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** $Date $Author $Comment
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** 02 Mar,2009 Lei Chuanhua Initial version
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*******************************************************************************/
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/*!
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\defgroup IFX_PCIE_MSI MSI OS APIs
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\ingroup IFX_PCIE
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\brief PCIe bus driver OS interface functions
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*/
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/*!
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\file ifxmips_pcie_msi.c
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\ingroup IFX_PCIE
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\brief PCIe MSI OS interface file
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/kernel_stat.h>
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <linux/module.h>
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#include <asm/bootinfo.h>
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#include <asm/irq.h>
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#include <asm/traps.h>
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#include "pcie-lantiq.h"
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#define IFX_MSI_IRQ_NUM 16
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#define SM(_v, _f) (((_v) << _f##_S) & (_f))
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#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000)
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#define IFX_PCIE_MSI_IR0 (INT_NUM_IM4_IRL0 + 27)
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#define IFX_PCIE_MSI_IR1 (INT_NUM_IM4_IRL0 + 28)
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#define IFX_PCIE_MSI_IR2 (INT_NUM_IM4_IRL0 + 29)
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#define IFX_PCIE_MSI_IR3 (INT_NUM_IM0_IRL0 + 30)
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#define IFX_MSI_PCI_INT_DISABLE 0x80000000
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#define IFX_MSI_PIC_INT_LINE 0x30000000
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#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000
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#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF
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#define IFX_MSI_PIC_BIG_ENDIAN 1
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#define IFX_MSI_PIC_INT_LINE_S 28
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#define IFX_MSI_PIC_MSG_ADDR_S 16
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#define IFX_MSI_PIC_MSG_DATA_S 0x0
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enum {
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IFX_PCIE_MSI_IDX0 = 0,
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IFX_PCIE_MSI_IDX1,
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IFX_PCIE_MSI_IDX2,
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IFX_PCIE_MSI_IDX3,
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};
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typedef struct ifx_msi_irq_idx {
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const int irq;
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const int idx;
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}ifx_msi_irq_idx_t;
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struct ifx_msi_pic {
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volatile u32 pic_table[IFX_MSI_IRQ_NUM];
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volatile u32 pic_endian; /* 0x40 */
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};
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typedef struct ifx_msi_pic *ifx_msi_pic_t;
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typedef struct ifx_msi_irq {
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const volatile ifx_msi_pic_t msi_pic_p;
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const u32 msi_phy_base;
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const ifx_msi_irq_idx_t msi_irq_idx[IFX_MSI_IRQ_NUM];
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/*
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* Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
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* in use.
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*/
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u16 msi_free_irq_bitmask;
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/*
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* Each bit in msi_multiple_irq_bitmask tells that the device using
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* this bit in msi_free_irq_bitmask is also using the next bit. This
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* is used so we can disable all of the MSI interrupts when a device
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* uses multiple.
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*/
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u16 msi_multiple_irq_bitmask;
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}ifx_msi_irq_t;
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static ifx_msi_irq_t msi_irqs[IFX_PCIE_CORE_NR] = {
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{
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.msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI_PIC_REG_BASE,
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.msi_phy_base = PCIE_MSI_PHY_BASE,
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.msi_irq_idx = {
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{IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
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{IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
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{IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
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{IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
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{IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
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{IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
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{IFX_PCIE_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE_MSI_IR1, IFX_PCIE_MSI_IDX1},
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{IFX_PCIE_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE_MSI_IR3, IFX_PCIE_MSI_IDX3},
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},
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.msi_free_irq_bitmask = 0,
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.msi_multiple_irq_bitmask= 0,
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},
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#ifdef CONFIG_IFX_PCIE_2ND_CORE
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{
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.msi_pic_p = (const volatile ifx_msi_pic_t)IFX_MSI1_PIC_REG_BASE,
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.msi_phy_base = PCIE1_MSI_PHY_BASE,
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.msi_irq_idx = {
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{IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
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{IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
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{IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
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{IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
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{IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
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{IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
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{IFX_PCIE1_MSI_IR0, IFX_PCIE_MSI_IDX0}, {IFX_PCIE1_MSI_IR1, IFX_PCIE_MSI_IDX1},
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{IFX_PCIE1_MSI_IR2, IFX_PCIE_MSI_IDX2}, {IFX_PCIE1_MSI_IR3, IFX_PCIE_MSI_IDX3},
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},
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.msi_free_irq_bitmask = 0,
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.msi_multiple_irq_bitmask= 0,
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},
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#endif /* CONFIG_IFX_PCIE_2ND_CORE */
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};
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/*
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* This lock controls updates to msi_free_irq_bitmask,
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* msi_multiple_irq_bitmask and pic register settting
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*/
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static DEFINE_SPINLOCK(ifx_pcie_msi_lock);
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void pcie_msi_pic_init(int pcie_port)
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{
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spin_lock(&ifx_pcie_msi_lock);
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msi_irqs[pcie_port].msi_pic_p->pic_endian = IFX_MSI_PIC_BIG_ENDIAN;
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spin_unlock(&ifx_pcie_msi_lock);
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}
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/**
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* \fn int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
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* \brief Called when a driver request MSI interrupts instead of the
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* legacy INT A-D. This routine will allocate multiple interrupts
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* for MSI devices that support them. A device can override this by
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* programming the MSI control bits [6:4] before calling
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* pci_enable_msi().
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*
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* \param[in] pdev Device requesting MSI interrupts
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* \param[in] desc MSI descriptor
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*
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* \return -EINVAL Invalid pcie root port or invalid msi bit
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* \return 0 OK
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* \ingroup IFX_PCIE_MSI
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*/
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int
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arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
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{
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int irq, pos;
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u16 control;
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int irq_idx;
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int irq_step;
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int configured_private_bits;
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int request_private_bits;
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struct msi_msg msg;
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u16 search_mask;
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struct ifx_pci_controller *ctrl = pdev->bus->sysdata;
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int pcie_port = ctrl->port;
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IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s %s enter\n", __func__, pci_name(pdev));
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/* XXX, skip RC MSI itself */
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if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT) {
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IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s RC itself doesn't use MSI interrupt\n", __func__);
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return -EINVAL;
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}
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/*
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* Read the MSI config to figure out how many IRQs this device
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* wants. Most devices only want 1, which will give
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* configured_private_bits and request_private_bits equal 0.
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*/
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pci_read_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, &control);
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/*
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* If the number of private bits has been configured then use
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* that value instead of the requested number. This gives the
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* driver the chance to override the number of interrupts
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* before calling pci_enable_msi().
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*/
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configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
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if (configured_private_bits == 0) {
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/* Nothing is configured, so use the hardware requested size */
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request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
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}
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else {
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/*
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* Use the number of configured bits, assuming the
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* driver wanted to override the hardware request
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* value.
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*/
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request_private_bits = configured_private_bits;
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}
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/*
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* The PCI 2.3 spec mandates that there are at most 32
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* interrupts. If this device asks for more, only give it one.
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*/
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if (request_private_bits > 5) {
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request_private_bits = 0;
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}
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again:
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/*
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* The IRQs have to be aligned on a power of two based on the
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* number being requested.
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*/
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irq_step = (1 << request_private_bits);
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/* Mask with one bit for each IRQ */
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search_mask = (1 << irq_step) - 1;
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/*
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* We're going to search msi_free_irq_bitmask_lock for zero
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* bits. This represents an MSI interrupt number that isn't in
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* use.
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*/
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spin_lock(&ifx_pcie_msi_lock);
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for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos += irq_step) {
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if ((msi_irqs[pcie_port].msi_free_irq_bitmask & (search_mask << pos)) == 0) {
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msi_irqs[pcie_port].msi_free_irq_bitmask |= search_mask << pos;
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msi_irqs[pcie_port].msi_multiple_irq_bitmask |= (search_mask >> 1) << pos;
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break;
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}
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}
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spin_unlock(&ifx_pcie_msi_lock);
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/* Make sure the search for available interrupts didn't fail */
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if (pos >= IFX_MSI_IRQ_NUM) {
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if (request_private_bits) {
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IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s: Unable to find %d free "
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"interrupts, trying just one", __func__, 1 << request_private_bits);
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request_private_bits = 0;
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goto again;
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}
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else {
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printk(KERN_ERR "%s: Unable to find a free MSI interrupt\n", __func__);
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return -EINVAL;
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}
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}
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irq = msi_irqs[pcie_port].msi_irq_idx[pos].irq;
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irq_idx = msi_irqs[pcie_port].msi_irq_idx[pos].idx;
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IFX_PCIE_PRINT(PCIE_MSG_MSI, "pos %d, irq %d irq_idx %d\n", pos, irq, irq_idx);
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/*
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* Initialize MSI. This has to match the memory-write endianess from the device
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* Address bits [23:12]
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*/
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spin_lock(&ifx_pcie_msi_lock);
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msi_irqs[pcie_port].msi_pic_p->pic_table[pos] = SM(irq_idx, IFX_MSI_PIC_INT_LINE) |
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SM((msi_irqs[pcie_port].msi_phy_base >> 12), IFX_MSI_PIC_MSG_ADDR) |
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SM((1 << pos), IFX_MSI_PIC_MSG_DATA);
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/* Enable this entry */
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msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~IFX_MSI_PCI_INT_DISABLE;
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spin_unlock(&ifx_pcie_msi_lock);
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IFX_PCIE_PRINT(PCIE_MSG_MSI, "pic_table[%d]: 0x%08x\n",
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pos, msi_irqs[pcie_port].msi_pic_p->pic_table[pos]);
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/* Update the number of IRQs the device has available to it */
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control &= ~PCI_MSI_FLAGS_QSIZE;
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control |= (request_private_bits << 4);
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pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS, control);
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irq_set_msi_desc(irq, desc);
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msg.address_hi = 0x0;
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msg.address_lo = msi_irqs[pcie_port].msi_phy_base;
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msg.data = SM((1 << pos), IFX_MSI_PIC_MSG_DATA);
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IFX_PCIE_PRINT(PCIE_MSG_MSI, "msi_data: pos %d 0x%08x\n", pos, msg.data);
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write_msi_msg(irq, &msg);
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IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__);
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return 0;
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}
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static int
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pcie_msi_irq_to_port(unsigned int irq, int *port)
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{
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int ret = 0;
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if (irq == IFX_PCIE_MSI_IR0 || irq == IFX_PCIE_MSI_IR1 ||
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irq == IFX_PCIE_MSI_IR2 || irq == IFX_PCIE_MSI_IR3) {
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*port = IFX_PCIE_PORT0;
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}
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#ifdef CONFIG_IFX_PCIE_2ND_CORE
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else if (irq == IFX_PCIE1_MSI_IR0 || irq == IFX_PCIE1_MSI_IR1 ||
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irq == IFX_PCIE1_MSI_IR2 || irq == IFX_PCIE1_MSI_IR3) {
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*port = IFX_PCIE_PORT1;
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}
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#endif /* CONFIG_IFX_PCIE_2ND_CORE */
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else {
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printk(KERN_ERR "%s: Attempted to teardown illegal "
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"MSI interrupt (%d)\n", __func__, irq);
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ret = -EINVAL;
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}
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return ret;
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}
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/**
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* \fn void arch_teardown_msi_irq(unsigned int irq)
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* \brief Called when a device no longer needs its MSI interrupts. All
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* MSI interrupts for the device are freed.
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*
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* \param irq The devices first irq number. There may be multple in sequence.
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* \return none
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* \ingroup IFX_PCIE_MSI
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*/
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void
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arch_teardown_msi_irq(unsigned int irq)
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{
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int pos;
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int number_irqs;
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u16 bitmask;
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int pcie_port;
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IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s enter\n", __func__);
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BUG_ON(irq > (INT_NUM_IM4_IRL0 + 31));
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if (pcie_msi_irq_to_port(irq, &pcie_port) != 0) {
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return;
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}
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/* Shift the mask to the correct bit location, not always correct
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* Probally, the first match will be chosen.
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*/
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for (pos = 0; pos < IFX_MSI_IRQ_NUM; pos++) {
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if ((msi_irqs[pcie_port].msi_irq_idx[pos].irq == irq)
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&& (msi_irqs[pcie_port].msi_free_irq_bitmask & ( 1 << pos))) {
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break;
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}
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}
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if (pos >= IFX_MSI_IRQ_NUM) {
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printk(KERN_ERR "%s: Unable to find a matched MSI interrupt\n", __func__);
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return;
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}
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spin_lock(&ifx_pcie_msi_lock);
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/* Disable this entry */
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msi_irqs[pcie_port].msi_pic_p->pic_table[pos] |= IFX_MSI_PCI_INT_DISABLE;
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msi_irqs[pcie_port].msi_pic_p->pic_table[pos] &= ~(IFX_MSI_PIC_INT_LINE | IFX_MSI_PIC_MSG_ADDR | IFX_MSI_PIC_MSG_DATA);
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spin_unlock(&ifx_pcie_msi_lock);
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/*
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* Count the number of IRQs we need to free by looking at the
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* msi_multiple_irq_bitmask. Each bit set means that the next
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* IRQ is also owned by this device.
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*/
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number_irqs = 0;
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while (((pos + number_irqs) < IFX_MSI_IRQ_NUM) &&
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(msi_irqs[pcie_port].msi_multiple_irq_bitmask & (1 << (pos + number_irqs)))) {
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number_irqs++;
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}
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number_irqs++;
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/* Mask with one bit for each IRQ */
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bitmask = (1 << number_irqs) - 1;
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bitmask <<= pos;
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if ((msi_irqs[pcie_port].msi_free_irq_bitmask & bitmask) != bitmask) {
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printk(KERN_ERR "%s: Attempted to teardown MSI "
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"interrupt (%d) not in use\n", __func__, irq);
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return;
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}
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/* Checks are done, update the in use bitmask */
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spin_lock(&ifx_pcie_msi_lock);
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msi_irqs[pcie_port].msi_free_irq_bitmask &= ~bitmask;
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msi_irqs[pcie_port].msi_multiple_irq_bitmask &= ~(bitmask >> 1);
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spin_unlock(&ifx_pcie_msi_lock);
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IFX_PCIE_PRINT(PCIE_MSG_MSI, "%s exit\n", __func__);
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}
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Chuanhua.Lei@infineon.com");
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MODULE_SUPPORTED_DEVICE("Infineon PCIe IP builtin MSI PIC module");
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MODULE_DESCRIPTION("Infineon PCIe IP builtin MSI PIC driver");
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