mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 16:31:13 +00:00
506 lines
13 KiB
Diff
506 lines
13 KiB
Diff
--- a/drivers/bcma/Kconfig
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+++ b/drivers/bcma/Kconfig
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@@ -38,6 +38,11 @@ config BCMA_HOST_SOC
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bool
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depends on BCMA_DRIVER_MIPS
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+config BCMA_SFLASH
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+ bool
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+ depends on BCMA_DRIVER_MIPS
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+ default y
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+
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config BCMA_DRIVER_MIPS
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bool "BCMA Broadcom MIPS core driver"
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depends on BCMA && MIPS
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--- a/drivers/bcma/Makefile
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+++ b/drivers/bcma/Makefile
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@@ -1,5 +1,6 @@
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bcma-y += main.o scan.o core.o sprom.o
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bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
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+bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
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bcma-y += driver_pci.o
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bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
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bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
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--- a/drivers/bcma/bcma_private.h
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+++ b/drivers/bcma/bcma_private.h
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@@ -42,6 +42,11 @@ void bcma_chipco_serial_init(struct bcma
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u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc);
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u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc);
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+#ifdef CONFIG_BCMA_SFLASH
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+/* driver_chipcommon_sflash.c */
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+int bcma_sflash_init(struct bcma_drv_cc *cc);
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+#endif /* CONFIG_BCMA_SFLASH */
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+
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#ifdef CONFIG_BCMA_HOST_PCI
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/* host_pci.c */
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extern int __init bcma_host_pci_init(void);
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--- /dev/null
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+++ b/drivers/bcma/driver_chipcommon_sflash.c
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@@ -0,0 +1,398 @@
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+/*
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+ * Broadcom SiliconBackplane chipcommon serial flash interface
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+ *
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+ * Copyright 2011, Jonas Gorski <jonas.gorski@gmail.com>
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+ * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
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+ * Copyright 2010, Broadcom Corporation
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+ *
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+ * Licensed under the GNU/GPL. See COPYING for details.
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+ */
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+
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+#include <linux/bcma/bcma.h>
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+#include <linux/bcma/bcma_driver_chipcommon.h>
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+#include <linux/delay.h>
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+
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+#include "bcma_private.h"
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+
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+#define NUM_RETRIES 3
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+
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+
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+/* Issue a serial flash command */
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+static inline void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
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+{
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+ bcma_cc_write32(cc, BCMA_CC_FLASHCTL,
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+ BCMA_CC_FLASHCTL_START | opcode);
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+ while (bcma_cc_read32(cc, BCMA_CC_FLASHCTL) & BCMA_CC_FLASHCTL_BUSY)
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+ ;
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+}
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+
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+
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+static inline void bcma_sflash_write_u8(struct bcma_drv_cc *cc,
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+ u32 offset, u8 byte)
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+{
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+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, offset);
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+ bcma_cc_write32(cc, BCMA_CC_FLASHDATA, byte);
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+}
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+
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+/* Initialize serial flash access */
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+int bcma_sflash_init(struct bcma_drv_cc *cc)
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+{
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+ u32 id, id2;
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+
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+ memset(&cc->sflash, 0, sizeof(struct bcma_sflash));
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+
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+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
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+ case BCMA_CC_FLASHT_STSER:
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+ /* Probe for ST chips */
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_DP);
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+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 0);
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
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+ id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
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+ cc->sflash.blocksize = 64 * 1024;
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+ switch (id) {
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+ case 0x11:
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+ /* ST M25P20 2 Mbit Serial Flash */
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+ cc->sflash.numblocks = 4;
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+ break;
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+ case 0x12:
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+ /* ST M25P40 4 Mbit Serial Flash */
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+ cc->sflash.numblocks = 8;
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+ break;
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+ case 0x13:
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+ /* ST M25P80 8 Mbit Serial Flash */
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+ cc->sflash.numblocks = 16;
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+ break;
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+ case 0x14:
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+ /* ST M25P16 16 Mbit Serial Flash */
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+ cc->sflash.numblocks = 32;
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+ break;
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+ case 0x15:
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+ /* ST M25P32 32 Mbit Serial Flash */
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+ cc->sflash.numblocks = 64;
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+ break;
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+ case 0x16:
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+ /* ST M25P64 64 Mbit Serial Flash */
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+ cc->sflash.numblocks = 128;
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+ break;
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+ case 0x17:
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+ /* ST M25FL128 128 Mbit Serial Flash */
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+ cc->sflash.numblocks = 256;
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+ break;
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+ case 0xbf:
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+ /* All of the following flashes are SST with
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+ * 4KB subsectors. Others should be added but
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+ * We'll have to revamp the way we identify them
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+ * since RES is not eough to disambiguate them.
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+ */
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+ cc->sflash.blocksize = 4 * 1024;
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+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, 1);
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RES);
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+ id2 = bcma_cc_read32(cc, BCMA_CC_FLASHDATA);
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+ switch (id2) {
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+ case 1:
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+ /* SST25WF512 512 Kbit Serial Flash */
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+ case 0x48:
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+ /* SST25VF512 512 Kbit Serial Flash */
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+ cc->sflash.numblocks = 16;
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+ break;
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+ case 2:
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+ /* SST25WF010 1 Mbit Serial Flash */
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+ case 0x49:
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+ /* SST25VF010 1 Mbit Serial Flash */
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+ cc->sflash.numblocks = 32;
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+ break;
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+ case 3:
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+ /* SST25WF020 2 Mbit Serial Flash */
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+ case 0x43:
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+ /* SST25VF020 2 Mbit Serial Flash */
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+ cc->sflash.numblocks = 64;
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+ break;
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+ case 4:
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+ /* SST25WF040 4 Mbit Serial Flash */
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+ case 0x44:
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+ /* SST25VF040 4 Mbit Serial Flash */
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+ case 0x8d:
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+ /* SST25VF040B 4 Mbit Serial Flash */
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+ cc->sflash.numblocks = 128;
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+ break;
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+ case 5:
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+ /* SST25WF080 8 Mbit Serial Flash */
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+ case 0x8e:
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+ /* SST25VF080B 8 Mbit Serial Flash */
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+ cc->sflash.numblocks = 256;
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+ break;
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+ case 0x41:
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+ /* SST25VF016 16 Mbit Serial Flash */
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+ cc->sflash.numblocks = 512;
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+ break;
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+ case 0x4a:
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+ /* SST25VF032 32 Mbit Serial Flash */
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+ cc->sflash.numblocks = 1024;
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+ break;
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+ case 0x4b:
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+ /* SST25VF064 64 Mbit Serial Flash */
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+ cc->sflash.numblocks = 2048;
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+ break;
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+ }
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+ break;
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+ }
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+ break;
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+
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+ case BCMA_CC_FLASHT_ATSER:
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+ /* Probe for Atmel chips */
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
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+ id = bcma_cc_read32(cc, BCMA_CC_FLASHDATA) & 0x3c;
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+ switch (id) {
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+ case 0xc:
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+ /* Atmel AT45DB011 1Mbit Serial Flash */
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+ cc->sflash.blocksize = 256;
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+ cc->sflash.numblocks = 512;
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+ break;
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+ case 0x14:
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+ /* Atmel AT45DB021 2Mbit Serial Flash */
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+ cc->sflash.blocksize = 256;
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+ cc->sflash.numblocks = 1024;
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+ break;
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+ case 0x1c:
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+ /* Atmel AT45DB041 4Mbit Serial Flash */
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+ cc->sflash.blocksize = 256;
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+ cc->sflash.numblocks = 2048;
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+ break;
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+ case 0x24:
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+ /* Atmel AT45DB081 8Mbit Serial Flash */
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+ cc->sflash.blocksize = 256;
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+ cc->sflash.numblocks = 4096;
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+ break;
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+ case 0x2c:
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+ /* Atmel AT45DB161 16Mbit Serial Flash */
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+ cc->sflash.blocksize = 512;
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+ cc->sflash.numblocks = 4096;
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+ break;
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+ case 0x34:
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+ /* Atmel AT45DB321 32Mbit Serial Flash */
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+ cc->sflash.blocksize = 512;
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+ cc->sflash.numblocks = 8192;
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+ break;
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+ case 0x3c:
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+ /* Atmel AT45DB642 64Mbit Serial Flash */
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+ cc->sflash.blocksize = 1024;
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+ cc->sflash.numblocks = 8192;
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+ break;
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+ }
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+ break;
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+ }
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+
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+ cc->sflash.size = cc->sflash.blocksize * cc->sflash.numblocks;
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+
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+ return cc->sflash.size ? 0 : -ENODEV;
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+}
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+
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+/* Read len bytes starting at offset into buf. Returns number of bytes read. */
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+int bcma_sflash_read(struct bcma_drv_cc *cc, u32 offset, u32 len, u8 *buf)
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+{
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+ u8 *from, *to;
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+ u32 cnt, i;
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+
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+ if (!len)
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+ return 0;
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+
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+ if ((offset + len) > cc->sflash.size)
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+ return -EINVAL;
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+
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+ if ((len >= 4) && (offset & 3))
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+ cnt = 4 - (offset & 3);
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+ else if ((len >= 4) && ((u32)buf & 3))
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+ cnt = 4 - ((u32)buf & 3);
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+ else
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+ cnt = len;
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+
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+ from = (u8 *)KSEG0ADDR(BCMA_FLASH2 + offset);
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+
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+ to = (u8 *)buf;
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+
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+ if (cnt < 4) {
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+ for (i = 0; i < cnt; i++) {
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+ *to = readb(from);
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+ from++;
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+ to++;
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+ }
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+ return cnt;
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+ }
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+
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+ while (cnt >= 4) {
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+ *(u32 *)to = readl(from);
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+ from += 4;
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+ to += 4;
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+ cnt -= 4;
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+ }
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+
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+ return len - cnt;
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+}
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+
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+/* Poll for command completion. Returns zero when complete. */
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+int bcma_sflash_poll(struct bcma_drv_cc *cc, u32 offset)
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+{
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+ if (offset >= cc->sflash.size)
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+ return -22;
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+
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+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
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+ case BCMA_CC_FLASHT_STSER:
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+ /* Check for ST Write In Progress bit */
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_RDSR);
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+ return bcma_cc_read32(cc, BCMA_CC_FLASHDATA)
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+ & BCMA_CC_FLASHDATA_ST_WIP;
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+ case BCMA_CC_FLASHT_ATSER:
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+ /* Check for Atmel Ready bit */
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_STATUS);
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+ return !(bcma_cc_read32(cc, BCMA_CC_FLASHDATA)
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+ & BCMA_CC_FLASHDATA_AT_READY);
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+ }
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+
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+ return 0;
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+}
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+
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+
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+static int sflash_st_write(struct bcma_drv_cc *cc, u32 offset, u32 len,
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+ const u8 *buf)
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+{
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+ int written = 1;
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+
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+ /* Enable writes */
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_WREN);
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+ bcma_sflash_write_u8(cc, offset, *buf++);
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+ /* Issue a page program with CSA bit set */
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_CSA | BCMA_CC_FLASHCTL_ST_PP);
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+ offset++;
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+ len--;
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+ while (len > 0) {
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+ if ((offset & 255) == 0) {
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+ /* Page boundary, poll droping cs and return */
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+ bcma_cc_write32(cc, BCMA_CC_FLASHCTL, 0);
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+ udelay(1);
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+ if (!bcma_sflash_poll(cc, offset)) {
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+ /* Flash rejected command */
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+ return -EAGAIN;
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+ }
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+ return written;
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+ } else {
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+ /* Write single byte */
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+ bcma_sflash_cmd(cc,
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+ BCMA_CC_FLASHCTL_ST_CSA |
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+ *buf++);
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+ }
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+ written++;
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+ offset++;
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+ len--;
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+ }
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+ /* All done, drop cs & poll */
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+ bcma_cc_write32(cc, BCMA_CC_FLASHCTL, 0);
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+ udelay(1);
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+ if (!bcma_sflash_poll(cc, offset)) {
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+ /* Flash rejected command */
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+ return -EAGAIN;
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+ }
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+ return written;
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+}
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+
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+static int sflash_at_write(struct bcma_drv_cc *cc, u32 offset, u32 len,
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+ const u8 *buf)
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+{
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+ struct bcma_sflash *sfl = &cc->sflash;
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+ u32 page, byte, mask;
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+ int ret = 0;
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+
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+ mask = sfl->blocksize - 1;
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+ page = (offset & ~mask) << 1;
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+ byte = offset & mask;
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+ /* Read main memory page into buffer 1 */
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+ if (byte || (len < sfl->blocksize)) {
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+ int i = 100;
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+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, page);
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_BUF1_LOAD);
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+ /* 250 us for AT45DB321B */
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+ while (i > 0 && bcma_sflash_poll(cc, offset)) {
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+ udelay(10);
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+ i--;
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+ }
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+ BUG_ON(!bcma_sflash_poll(cc, offset));
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+ }
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+ /* Write into buffer 1 */
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+ for (ret = 0; (ret < (int)len) && (byte < sfl->blocksize); ret++) {
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+ bcma_sflash_write_u8(cc, byte++, *buf++);
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_BUF1_WRITE);
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+ }
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+ /* Write buffer 1 into main memory page */
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+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, page);
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_BUF1_PROGRAM);
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+
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+ return ret;
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+}
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+
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+/* Write len bytes starting at offset into buf. Returns number of bytes
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+ * written. Caller should poll for completion.
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+ */
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+int bcma_sflash_write(struct bcma_drv_cc *cc, u32 offset, u32 len,
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+ const u8 *buf)
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+{
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+ struct bcma_sflash *sfl;
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+ int ret = 0, tries = NUM_RETRIES;
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+
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+ if (!len)
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+ return 0;
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+
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+ if ((offset + len) > cc->sflash.size)
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+ return -EINVAL;
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+
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+ sfl = &cc->sflash;
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+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
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+ case BCMA_CC_FLASHT_STSER:
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+ do {
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+ ret = sflash_st_write(cc, offset, len, buf);
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+ tries--;
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+ } while (ret == -EAGAIN && tries > 0);
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+
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+ if (ret == -EAGAIN && tries == 0) {
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+ pr_info("ST Flash rejected write\n");
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+ ret = -EIO;
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+ }
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+ break;
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+ case BCMA_CC_FLASHT_ATSER:
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+ ret = sflash_at_write(cc, offset, len, buf);
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+ break;
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+ }
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+
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+ return ret;
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+}
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+
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+/* Erase a region. Returns number of bytes scheduled for erasure.
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+ * Caller should poll for completion.
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+ */
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+int bcma_sflash_erase(struct bcma_drv_cc *cc, u32 offset)
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+{
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+ struct bcma_sflash *sfl;
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+
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+ if (offset >= cc->sflash.size)
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+ return -EINVAL;
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+
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+ sfl = &cc->sflash;
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+ switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
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+ case BCMA_CC_FLASHT_STSER:
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_WREN);
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+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, offset);
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+ /* Newer flashes have "sub-sectors" which can be erased independently
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+ * with a new command: ST_SSE. The ST_SE command erases 64KB just as
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+ * before.
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+ */
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+ if (sfl->blocksize < (64 * 1024))
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_SSE);
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+ else
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_ST_SE);
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+ return sfl->blocksize;
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+ case BCMA_CC_FLASHT_ATSER:
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+ bcma_cc_write32(cc, BCMA_CC_FLASHADDR, offset << 1);
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+ bcma_sflash_cmd(cc, BCMA_CC_FLASHCTL_AT_PAGE_ERASE);
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+ return sfl->blocksize;
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+ }
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+
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+ return 0;
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+}
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--- a/drivers/bcma/driver_mips.c
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+++ b/drivers/bcma/driver_mips.c
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@@ -185,7 +185,13 @@ static void bcma_core_mips_flash_detect(
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switch (bus->drv_cc.capabilities & BCMA_CC_CAP_FLASHT) {
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case BCMA_CC_FLASHT_STSER:
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case BCMA_CC_FLASHT_ATSER:
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- pr_err("Serial flash not supported.\n");
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+#ifdef CONFIG_BCMA_SFLASH
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+ pr_info("found serial flash.\n");
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+ bus->drv_cc.flash_type = BCMA_SFLASH;
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+ bcma_sflash_init(&bus->drv_cc);
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+#else
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+ pr_info("serial flash not supported.\n");
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+#endif /* CONFIG_BCMA_SFLASH */
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break;
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case BCMA_CC_FLASHT_PARA:
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pr_info("found parallel flash.\n");
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--- a/include/linux/bcma/bcma_driver_chipcommon.h
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+++ b/include/linux/bcma/bcma_driver_chipcommon.h
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@@ -399,6 +399,7 @@ struct bcma_chipcommon_pmu {
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#ifdef CONFIG_BCMA_DRIVER_MIPS
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enum bcma_flash_type {
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BCMA_PFLASH,
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+ BCMA_SFLASH,
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};
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struct bcma_pflash {
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@@ -407,6 +408,14 @@ struct bcma_pflash {
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u32 window_size;
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};
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+#ifdef CONFIG_BCMA_SFLASH
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+struct bcma_sflash {
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+ u32 blocksize; /* Block size */
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+ u32 numblocks; /* Number of blocks */
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+ u32 size; /* Total size in bytes */
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+};
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+#endif /* CONFIG_BCMA_SFLASH */
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+
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struct bcma_serial_port {
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void *regs;
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unsigned long clockspeed;
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@@ -429,6 +438,9 @@ struct bcma_drv_cc {
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enum bcma_flash_type flash_type;
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union {
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struct bcma_pflash pflash;
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+#ifdef CONFIG_BCMA_SFLASH
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+ struct bcma_sflash sflash;
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+#endif /* CONFIG_BCMA_SFLASH */
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};
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int nr_serial_ports;
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@@ -483,4 +495,14 @@ extern void bcma_chipco_chipctl_maskset(
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extern void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc,
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u32 offset, u32 mask, u32 set);
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+#ifdef CONFIG_BCMA_SFLASH
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+/* Chipcommon sflash support. */
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+int bcma_sflash_read(struct bcma_drv_cc *cc, u32 offset, u32 len,
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+ u8 *buf);
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+int bcma_sflash_poll(struct bcma_drv_cc *cc, u32 offset);
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+int bcma_sflash_write(struct bcma_drv_cc *cc, u32 offset, u32 len,
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+ const u8 *buf);
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+int bcma_sflash_erase(struct bcma_drv_cc *cc, u32 offset);
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+#endif /* CONFIG_BCMA_SFLASH */
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+
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#endif /* LINUX_BCMA_DRIVER_CC_H_ */
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