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2d5ee43dc6
Manually rebased generic/pending-5.4/680-NET-skip-GRO-for-foreign-MAC-addresses.patch All others updated automatically. Compile-tested on: ramips/mt7621, armvirt/32 Runtime-tested on: ramips/mt7621, armvirt/32 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
65 lines
2.0 KiB
Diff
65 lines
2.0 KiB
Diff
From 121cd10d9ec4466b09ac33986c7b4c1f8eff9363 Mon Sep 17 00:00:00 2001
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From: Kuldeep Singh <kuldeep.singh@nxp.com>
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Date: Wed, 18 Dec 2019 15:09:41 +0530
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Subject: [PATCH] arm64: dts: ls208xa: Update qspi node properties for
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LS2088ARDB
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LS2088ADB has one spansion flash s25fs512s of size 64M.
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Update qspi dts entry for the board using compatibles as "jedec,spi-nor"
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to probe flash successfully. Also, align properties with other board dts
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properties.
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Since device properties are different, so remove fsl, ls1021a-qspi.
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ls1021a-qspi is to be used only for Big-endian verion of QSPI
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controller. Use dt-bindings constants in interrupts instead of using
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numbers.
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Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
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---
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arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 8 ++++----
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arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 6 +++---
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2 files changed, 7 insertions(+), 7 deletions(-)
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--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
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@@ -110,12 +110,12 @@
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&qspi {
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status = "okay";
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- flash0: s25fs512s@0 {
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+
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+ s25fs512s0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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- compatible = "spansion,m25p80";
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- m25p,fast-read;
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- spi-max-frequency = <20000000>;
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+ compatible = "jedec,spi-nor";
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+ spi-max-frequency = <50000000>;
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reg = <0>;
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};
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};
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--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
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+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
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@@ -609,16 +609,16 @@
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};
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qspi: spi@20c0000 {
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- status = "disabled";
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- compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
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+ compatible = "fsl,ls2080a-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x20c0000 0x0 0x10000>,
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<0x0 0x20000000 0x0 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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- interrupts = <0 25 0x4>; /* Level high type */
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+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clockgen 4 3>, <&clockgen 4 3>;
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clock-names = "qspi_en", "qspi";
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+ status = "disabled";
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};
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pcie1: pcie@3400000 {
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