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14940aee45
Removed upstreamed: target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch target/linux/mvebu/patches-5.4/020-arm64-dts-marvell-armada-37xx-Set-pcie_reset_pin-to-.patch The following patch does not apply to upstream any more and needs some more work to make it work fully again. I am not sure if we are still able to set the UART to a none standard baud rate. target/linux/ath79/patches-5.4/921-serial-core-add-support-for-boot-console-with-arbitr.patch These patches needed manually changes: target/linux/generic/pending-5.4/110-ehci_hcd_ignore_oc.patch target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch target/linux/layerscape/patches-5.4/804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch All others updated automatically. Compile-tested on: malta/le, armvirt/64, lantiq/xrx200 Runtime-tested on: malta/le, armvirt/64, lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
61 lines
1.8 KiB
Diff
61 lines
1.8 KiB
Diff
From 67ca04147efac6cac3f7490c61c817a84daada57 Mon Sep 17 00:00:00 2001
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From: Yangbo Lu <yangbo.lu@nxp.com>
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Date: Thu, 28 Nov 2019 14:42:44 +0800
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Subject: [PATCH] LF-368 net: mscc: ocelot: add VCAP IS2 rule to trap PTP
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Ethernet frames
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All the PTP messages over Ethernet have etype 0x88f7 on them.
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Use etype as the key to trap PTP messages.
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Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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---
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drivers/net/ethernet/mscc/ocelot.c | 23 +++++++++++++++++++++++
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1 file changed, 23 insertions(+)
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--- a/drivers/net/ethernet/mscc/ocelot.c
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+++ b/drivers/net/ethernet/mscc/ocelot.c
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@@ -2337,6 +2337,20 @@ void ocelot_set_cpu_port(struct ocelot *
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}
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EXPORT_SYMBOL(ocelot_set_cpu_port);
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+/* Entry for PTP over Ethernet (etype 0x88f7)
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+ * Action: trap to CPU port
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+ */
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+static struct ocelot_ace_rule ptp_rule = {
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+ .prio = 1,
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+ .type = OCELOT_ACE_TYPE_ETYPE,
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+ .dmac_mc = OCELOT_VCAP_BIT_1,
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+ .action = OCELOT_ACL_ACTION_TRAP,
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+ .frame.etype.etype.value[0] = 0x88,
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+ .frame.etype.etype.value[1] = 0xf7,
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+ .frame.etype.etype.mask[0] = 0xff,
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+ .frame.etype.etype.mask[1] = 0xff,
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+};
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+
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int ocelot_init(struct ocelot *ocelot)
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{
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char queue_name[32];
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@@ -2474,6 +2488,13 @@ int ocelot_init(struct ocelot *ocelot)
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"Timestamp initialization failed\n");
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return ret;
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}
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+
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+ /* Available on all ingress port except CPU port */
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+ ptp_rule.ocelot = ocelot;
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+ ptp_rule.ingress_port_mask =
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+ GENMASK(ocelot->num_phys_ports - 1, 0);
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+ ptp_rule.ingress_port_mask &= ~BIT(ocelot->cpu);
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+ ocelot_ace_rule_offload_add(&ptp_rule);
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}
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return 0;
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@@ -2488,6 +2509,8 @@ void ocelot_deinit(struct ocelot *ocelot
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cancel_delayed_work(&ocelot->stats_work);
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destroy_workqueue(ocelot->stats_queue);
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mutex_destroy(&ocelot->stats_lock);
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+ if (ocelot->ptp)
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+ ocelot_ace_rule_offload_del(&ptp_rule);
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ocelot_ace_deinit();
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if (ocelot->ptp_clock)
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ptp_clock_unregister(ocelot->ptp_clock);
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