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https://github.com/openwrt/openwrt.git
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1db4135e32
Adds preliminary kernel 4.9 support for this target. - Refreshed/Updated all patches Added 3 new patches: - 093 --> Add virtual PCI MMIO mapping - 230 --> Remove deprecated code - 240 --> Rework AT24 eeprom code to use the new NVMEM API Compiled & tested on cns3xxx (gw2388) Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
70 lines
1.6 KiB
Diff
70 lines
1.6 KiB
Diff
--- a/arch/arm/mach-cns3xxx/core.c
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+++ b/arch/arm/mach-cns3xxx/core.c
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@@ -307,13 +307,26 @@ void __init cns3xxx_timer_init(void)
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#ifdef CONFIG_CACHE_L2X0
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-void __init cns3xxx_l2x0_init(void)
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+static int cns3xxx_l2x0_enable = 1;
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+
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+static int __init cns3xxx_l2x0_disable(char *s)
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+{
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+ cns3xxx_l2x0_enable = 0;
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+ return 1;
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+}
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+__setup("nol2x0", cns3xxx_l2x0_disable);
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+
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+static int __init cns3xxx_l2x0_init(void)
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{
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- void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
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+ void __iomem *base;
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u32 val;
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+ if (!cns3xxx_l2x0_enable)
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+ return 0;
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+
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+ base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
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if (WARN_ON(!base))
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- return;
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+ return 0;
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/*
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* Tag RAM Control register
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@@ -343,7 +356,10 @@ void __init cns3xxx_l2x0_init(void)
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/* 32 KiB, 8-way, parity disable */
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l2x0_init(base, 0x00500000, 0xfe0f0fff);
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+
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+ return 0;
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}
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+arch_initcall(cns3xxx_l2x0_init);
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#endif /* CONFIG_CACHE_L2X0 */
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--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -239,8 +239,6 @@ static struct platform_device *cns3420_p
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static void __init cns3420_init(void)
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{
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- cns3xxx_l2x0_init();
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-
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platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
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cns3xxx_ahci_init();
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--- a/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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@@ -16,12 +16,6 @@
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extern struct smp_operations cns3xxx_smp_ops;
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extern void cns3xxx_timer_init(void);
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-#ifdef CONFIG_CACHE_L2X0
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-void __init cns3xxx_l2x0_init(void);
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-#else
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-static inline void cns3xxx_l2x0_init(void) {}
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-#endif /* CONFIG_CACHE_L2X0 */
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-
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#ifdef CONFIG_PCI
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extern void __init cns3xxx_pcie_init_late(void);
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#else
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