mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 06:08:08 +00:00
64b53247c4
Refresh patches. Remove upstreamed patch: generic/pending/181-net-usb-add-lte-modem-wistron-neweb-d18q1.patch Update patches that no longer applies: generic/hack/901-debloat_sock_diag.patch Compile-tested on: x86/64. Runtime-tested on: x86/64. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
46 lines
1.4 KiB
Diff
46 lines
1.4 KiB
Diff
From 79d0293e8f35e87b1f068fc0b7963a86ba56800e Mon Sep 17 00:00:00 2001
|
|
From: Sean Wang <sean.wang@mediatek.com>
|
|
Date: Thu, 28 Dec 2017 15:46:42 +0800
|
|
Subject: [PATCH 211/224] arm64: dts: mt7622: add power domain controller
|
|
device nodes
|
|
|
|
add power domain controller nodes
|
|
|
|
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
|
|
Cc: Matthias Brugger <matthias.bgg@gmail.com>
|
|
---
|
|
arch/arm64/boot/dts/mediatek/mt7622.dtsi | 15 +++++++++++++++
|
|
1 file changed, 15 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
|
+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
|
|
@@ -9,6 +9,7 @@
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/mt7622-clk.h>
|
|
+#include <dt-bindings/power/mt7622-power.h>
|
|
#include <dt-bindings/reset/mt7622-reset.h>
|
|
|
|
/ {
|
|
@@ -109,6 +110,20 @@
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
+ scpsys: scpsys@10006000 {
|
|
+ compatible = "mediatek,mt7622-scpsys",
|
|
+ "syscon";
|
|
+ #power-domain-cells = <1>;
|
|
+ reg = <0 0x10006000 0 0x1000>;
|
|
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
|
|
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
|
|
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
|
|
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
|
|
+ infracfg = <&infracfg>;
|
|
+ clocks = <&topckgen CLK_TOP_HIF_SEL>;
|
|
+ clock-names = "hif_sel";
|
|
+ };
|
|
+
|
|
sysirq: interrupt-controller@10200620 {
|
|
compatible = "mediatek,mt7622-sysirq",
|
|
"mediatek,mt6577-sysirq";
|