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102cb4742c
Refresh patches on all 4.4 supported platforms. 077-0005-bgmac-stop-clearing-DMA-receive-control-register-rig.patch removed as now upstream. Compile & run tested: ar71xx - Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
101 lines
3.0 KiB
Diff
101 lines
3.0 KiB
Diff
From f59dcab176293b646e1358144c93c58c3cda2813 Mon Sep 17 00:00:00 2001
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From: Felipe Balbi <felipe.balbi@linux.intel.com>
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Date: Fri, 11 Mar 2016 10:51:52 +0200
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Subject: usb: dwc3: core: improve reset sequence
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According to Synopsys Databook, we shouldn't be
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relying on GCTL.CORESOFTRESET bit as that's only for
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debugging purposes. Instead, let's use DCTL.CSFTRST
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if we're OTG or PERIPHERAL mode.
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Host side block will be reset by XHCI driver if
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necessary. Note that this reduces amount of time
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spent on dwc3_probe() by a long margin.
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We're still gonna wait for reset to finish for a
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long time (default to 1ms max), but tests show that
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the reset polling loop executed at most 19 times
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(modprobe dwc3 && modprobe -r dwc3 executed 1000
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times in a row).
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Suggested-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com>
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Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
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---
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drivers/usb/dwc3/core.c | 48 ++++++++++++++++++------------------------------
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1 file changed, 18 insertions(+), 30 deletions(-)
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--- a/drivers/usb/dwc3/core.c
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+++ b/drivers/usb/dwc3/core.c
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@@ -67,23 +67,9 @@ void dwc3_set_mode(struct dwc3 *dwc, u32
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static int dwc3_core_soft_reset(struct dwc3 *dwc)
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{
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u32 reg;
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+ int retries = 1000;
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int ret;
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- /* Before Resetting PHY, put Core in Reset */
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- reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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- reg |= DWC3_GCTL_CORESOFTRESET;
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- dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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-
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- /* Assert USB3 PHY reset */
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- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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- reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
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- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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-
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- /* Assert USB2 PHY reset */
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- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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- reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
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- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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-
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usb_phy_init(dwc->usb2_phy);
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usb_phy_init(dwc->usb3_phy);
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ret = phy_init(dwc->usb2_generic_phy);
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@@ -95,26 +81,28 @@ static int dwc3_core_soft_reset(struct d
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phy_exit(dwc->usb2_generic_phy);
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return ret;
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}
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- mdelay(100);
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- /* Clear USB3 PHY reset */
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- reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
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- reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
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- dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
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-
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- /* Clear USB2 PHY reset */
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- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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- reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
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- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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-
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- mdelay(100);
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-
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- /* After PHYs are stable we can take Core out of reset state */
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- reg = dwc3_readl(dwc->regs, DWC3_GCTL);
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- reg &= ~DWC3_GCTL_CORESOFTRESET;
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- dwc3_writel(dwc->regs, DWC3_GCTL, reg);
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+ /*
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+ * We're resetting only the device side because, if we're in host mode,
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+ * XHCI driver will reset the host block. If dwc3 was configured for
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+ * host-only mode, then we can return early.
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+ */
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+ if (dwc->dr_mode == USB_DR_MODE_HOST)
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+ return 0;
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+
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+ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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+ reg |= DWC3_DCTL_CSFTRST;
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+ dwc3_writel(dwc->regs, DWC3_DCTL, reg);
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+
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+ do {
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+ reg = dwc3_readl(dwc->regs, DWC3_DCTL);
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+ if (!(reg & DWC3_DCTL_CSFTRST))
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+ return 0;
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+
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+ udelay(1);
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+ } while (--retries);
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- return 0;
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+ return -ETIMEDOUT;
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}
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/**
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