ExternalVendorCode/openwrt
1
0
Fork 0
mirror of https://github.com/openwrt/openwrt.git synced 2024-12-22 23:12:32 +00:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity
1cd6237979
openwrt/target/linux/generic/patches-3.3/020-ssb_update.patch
Hauke Mehrtens bd9fa13c73 kernel: ssb/bcma: update to version from wireless-testing tag master-2012-07-02 
SVN-Revision: 32580
2012-07-02 23:12:58 +00:00

838 lines
29 KiB
Diff
Raw Blame History

--- a/drivers/ssb/b43_pci_bridge.c
+++ b/drivers/ssb/b43_pci_bridge.c
@@ -29,11 +29,14 @@ static const struct pci_device_id b43_pc
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
{ PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
+ { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
{ 0, },
};
MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
--- a/drivers/ssb/driver_chipcommon_pmu.c
+++ b/drivers/ssb/driver_chipcommon_pmu.c
@@ -13,6 +13,9 @@
#include <linux/ssb/ssb_driver_chipcommon.h>
#include <linux/delay.h>
#include <linux/export.h>
+#ifdef CONFIG_BCM47XX
+#include <asm/mach-bcm47xx/nvram.h>
+#endif
#include "ssb_private.h"
@@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
u32 pmuctl, tmp, pllctl;
unsigned int i;
- if ((bus->chip_id == 0x5354) && !crystalfreq) {
- /* The 5354 crystal freq is 25MHz */
- crystalfreq = 25000;
- }
if (crystalfreq)
e = pmu0_plltab_find_entry(crystalfreq);
if (!e)
@@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
if (bus->bustype == SSB_BUSTYPE_SSB) {
- /* TODO: The user may override the crystal frequency. */
+#ifdef CONFIG_BCM47XX
+ char buf[20];
+ if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
+ crystalfreq = simple_strtoul(buf, NULL, 0);
+#endif
}
switch (bus->chip_id) {
@@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
ssb_pmu1_pllinit_r0(cc, crystalfreq);
break;
case 0x4328:
+ ssb_pmu0_pllinit_r0(cc, crystalfreq);
+ break;
case 0x5354:
+ if (crystalfreq == 0)
+ crystalfreq = 25000;
ssb_pmu0_pllinit_r0(cc, crystalfreq);
break;
case 0x4322:
@@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
+
+u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
+{
+ struct ssb_bus *bus = cc->dev->bus;
+
+ switch (bus->chip_id) {
+ case 0x5354:
+ /* 5354 chip uses a non programmable PLL of frequency 240MHz */
+ return 240000000;
+ default:
+ ssb_printk(KERN_ERR PFX
+ "ERROR: PMU cpu clock unknown for device %04X\n",
+ bus->chip_id);
+ return 0;
+ }
+}
+
+u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
+{
+ struct ssb_bus *bus = cc->dev->bus;
+
+ switch (bus->chip_id) {
+ case 0x5354:
+ return 120000000;
+ default:
+ ssb_printk(KERN_ERR PFX
+ "ERROR: PMU controlclock unknown for device %04X\n",
+ bus->chip_id);
+ return 0;
+ }
+}
--- a/drivers/ssb/driver_mipscore.c
+++ b/drivers/ssb/driver_mipscore.c
@@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
struct ssb_bus *bus = mcore->dev->bus;
u32 pll_type, n, m, rate = 0;
+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
+ return ssb_pmu_get_cpu_clock(&bus->chipco);
+
if (bus->extif.dev) {
ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
} else if (bus->chipco.dev) {
--- a/drivers/ssb/main.c
+++ b/drivers/ssb/main.c
@@ -140,19 +140,6 @@ static void ssb_device_put(struct ssb_de
put_device(dev->dev);
}
-static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
-{
- if (drv)
- get_driver(&drv->drv);
- return drv;
-}
-
-static inline void ssb_driver_put(struct ssb_driver *drv)
-{
- if (drv)
- put_driver(&drv->drv);
-}
-
static int ssb_device_resume(struct device *dev)
{
struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
@@ -250,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
ssb_device_put(sdev);
continue;
}
- sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
- if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
- ssb_device_put(sdev);
+ sdrv = drv_to_ssb_drv(sdev->dev->driver);
+ if (SSB_WARN_ON(!sdrv->remove))
continue;
- }
sdrv->remove(sdev);
ctx->device_frozen[i] = 1;
}
@@ -293,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
dev_name(sdev->dev));
result = err;
}
- ssb_driver_put(sdrv);
ssb_device_put(sdev);
}
@@ -1094,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
u32 plltype;
u32 clkctl_n, clkctl_m;
+ if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
+ return ssb_pmu_get_controlclock(&bus->chipco);
+
if (ssb_extif_available(&bus->extif))
ssb_extif_get_clockcontrol(&bus->extif, &plltype,
&clkctl_n, &clkctl_m);
--- a/drivers/ssb/pci.c
+++ b/drivers/ssb/pci.c
@@ -178,6 +178,18 @@ err_pci:
#define SPEX(_outvar, _offset, _mask, _shift) \
SPEX16(_outvar, _offset, _mask, _shift)
+#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
+ do { \
+ SPEX(_field[0], _offset + 0, _mask, _shift); \
+ SPEX(_field[1], _offset + 2, _mask, _shift); \
+ SPEX(_field[2], _offset + 4, _mask, _shift); \
+ SPEX(_field[3], _offset + 6, _mask, _shift); \
+ SPEX(_field[4], _offset + 8, _mask, _shift); \
+ SPEX(_field[5], _offset + 10, _mask, _shift); \
+ SPEX(_field[6], _offset + 12, _mask, _shift); \
+ SPEX(_field[7], _offset + 14, _mask, _shift); \
+ } while (0)
+
static inline u8 ssb_crc8(u8 crc, u8 data)
{
@@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss
{
int i;
u16 v;
- s8 gain;
u16 loc[3];
if (out->revision == 3) /* rev 3 moved MAC */
@@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss
SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
- SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
- SSB_SPROM1_BINF_CCODE_SHIFT);
+ if (out->revision == 1)
+ SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
+ SSB_SPROM1_BINF_CCODE_SHIFT);
SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
SSB_SPROM1_BINF_ANTA_SHIFT);
SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
@@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss
SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
if (out->revision >= 2)
SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
+ SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
+ SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
/* Extract the antenna gain values. */
- gain = r123_extract_antgain(out->revision, in,
- SSB_SPROM1_AGAIN_BG,
- SSB_SPROM1_AGAIN_BG_SHIFT);
- out->antenna_gain.ghz24.a0 = gain;
- out->antenna_gain.ghz24.a1 = gain;
- out->antenna_gain.ghz24.a2 = gain;
- out->antenna_gain.ghz24.a3 = gain;
- gain = r123_extract_antgain(out->revision, in,
- SSB_SPROM1_AGAIN_A,
- SSB_SPROM1_AGAIN_A_SHIFT);
- out->antenna_gain.ghz5.a0 = gain;
- out->antenna_gain.ghz5.a1 = gain;
- out->antenna_gain.ghz5.a2 = gain;
- out->antenna_gain.ghz5.a3 = gain;
+ out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
+ SSB_SPROM1_AGAIN_BG,
+ SSB_SPROM1_AGAIN_BG_SHIFT);
+ out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
+ SSB_SPROM1_AGAIN_A,
+ SSB_SPROM1_AGAIN_A_SHIFT);
}
/* Revs 4 5 and 8 have partially shared layout */
@@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb
SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
SSB_SPROM4_ETHPHY_ET1A_SHIFT);
+ SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
if (out->revision == 4) {
- SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
+ SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
+ SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
} else {
- SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
+ SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
+ SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
@@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb
}
/* Extract the antenna gain values. */
- SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
+ SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
- SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
+ SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
- SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
+ SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
- SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
+ SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
- sizeof(out->antenna_gain.ghz5));
sprom_extract_r458(out, in);
@@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb
static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
{
int i;
- u16 v;
+ u16 v, o;
+ u16 pwr_info_offset[] = {
+ SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
+ SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
+ };
+ BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
+ ARRAY_SIZE(out->core_pwr_info));
/* extract the MAC address */
for (i = 0; i < 3; i++) {
v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
*(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
}
- SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
+ SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
+ SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
+ SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
@@ -596,16 +611,46 @@ static void sprom_extract_r8(struct ssb_
SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
/* Extract the antenna gain values. */
- SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
+ SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
- SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
+ SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
- SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
+ SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
- SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
+ SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
- memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
- sizeof(out->antenna_gain.ghz5));
+
+ /* Extract cores power info info */
+ for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
+ o = pwr_info_offset[i];
+ SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
+ SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
+ SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
+ SSB_SPROM8_2G_MAXP, 0);
+
+ SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
+ SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
+ SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
+
+ SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
+ SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
+ SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
+ SSB_SPROM8_5G_MAXP, 0);
+ SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
+ SSB_SPROM8_5GH_MAXP, 0);
+ SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
+ SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
+
+ SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
+ SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
+ SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
+ SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
+ SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
+ SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
+ SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
+ SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
+ SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
+ }
/* Extract FEM info */
SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
@@ -630,6 +675,63 @@ static void sprom_extract_r8(struct ssb_
SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
+ SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
+ SSB_SPROM8_LEDDC_ON_SHIFT);
+ SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
+ SSB_SPROM8_LEDDC_OFF_SHIFT);
+
+ SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
+ SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
+ SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
+ SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
+ SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
+ SSB_SPROM8_TXRXC_SWITCH_SHIFT);
+
+ SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
+
+ SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
+ SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
+ SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
+ SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
+
+ SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
+ SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
+ SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
+ SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
+ SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
+ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
+ SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
+ SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
+ SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
+ SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
+ SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
+ SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
+ SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
+ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
+ SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
+ SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
+ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
+ SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
+ SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
+ SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
+
+ SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
+ SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
+ SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
+ SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
+
+ SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
+ SSB_SPROM8_THERMAL_TRESH_SHIFT);
+ SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
+ SSB_SPROM8_THERMAL_OFFSET_SHIFT);
+ SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
+ SSB_SPROM8_TEMPDELTA_PHYCAL,
+ SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
+ SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
+ SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
+ SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
+ SSB_SPROM8_TEMPDELTA_HYSTERESIS,
+ SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
sprom_extract_r458(out, in);
/* TODO - get remaining rev 8 stuff needed */
@@ -759,7 +861,6 @@ static void ssb_pci_get_boardinfo(struct
{
bi->vendor = bus->host_pci->subsystem_vendor;
bi->type = bus->host_pci->subsystem_device;
- bi->rev = bus->host_pci->revision;
}
int ssb_pci_get_invariants(struct ssb_bus *bus,
--- a/drivers/ssb/pcmcia.c
+++ b/drivers/ssb/pcmcia.c
@@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
case SSB_PCMCIA_CIS_ANTGAIN:
GOTO_ERROR_ON(tuple->TupleDataLen != 2,
"antg tpl size");
- sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
- sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
- sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
- sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
- sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
- sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
- sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
- sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
+ sprom->antenna_gain.a0 = tuple->TupleData[1];
+ sprom->antenna_gain.a1 = tuple->TupleData[1];
+ sprom->antenna_gain.a2 = tuple->TupleData[1];
+ sprom->antenna_gain.a3 = tuple->TupleData[1];
break;
case SSB_PCMCIA_CIS_BFLAGS:
GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
--- a/drivers/ssb/scan.c
+++ b/drivers/ssb/scan.c
@@ -90,6 +90,8 @@ const char *ssb_core_name(u16 coreid)
return "ARM 1176";
case SSB_DEV_ARM_7TDMI:
return "ARM 7TDMI";
+ case SSB_DEV_ARM_CM3:
+ return "ARM Cortex M3";
}
return "UNKNOWN";
}
@@ -318,6 +320,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
bus->chip_package = 0;
}
}
+ ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
+ "package 0x%02X\n", bus->chip_id, bus->chip_rev,
+ bus->chip_package);
if (!bus->nr_devices)
bus->nr_devices = chipid_to_nrcores(bus->chip_id);
if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
--- a/drivers/ssb/sdio.c
+++ b/drivers/ssb/sdio.c
@@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
case SSB_SDIO_CIS_ANTGAIN:
GOTO_ERROR_ON(tuple->size != 2,
"antg tpl size");
- sprom->antenna_gain.ghz24.a0 = tuple->data[1];
- sprom->antenna_gain.ghz24.a1 = tuple->data[1];
- sprom->antenna_gain.ghz24.a2 = tuple->data[1];
- sprom->antenna_gain.ghz24.a3 = tuple->data[1];
- sprom->antenna_gain.ghz5.a0 = tuple->data[1];
- sprom->antenna_gain.ghz5.a1 = tuple->data[1];
- sprom->antenna_gain.ghz5.a2 = tuple->data[1];
- sprom->antenna_gain.ghz5.a3 = tuple->data[1];
+ sprom->antenna_gain.a0 = tuple->data[1];
+ sprom->antenna_gain.a1 = tuple->data[1];
+ sprom->antenna_gain.a2 = tuple->data[1];
+ sprom->antenna_gain.a3 = tuple->data[1];
break;
case SSB_SDIO_CIS_BFLAGS:
GOTO_ERROR_ON((tuple->size != 3) &&
--- a/drivers/ssb/ssb_private.h
+++ b/drivers/ssb/ssb_private.h
@@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
}
#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
+/* driver_chipcommon_pmu.c */
+extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
+extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
+
#endif /* LINUX_SSB_PRIVATE_H_ */
--- a/include/linux/ssb/ssb.h
+++ b/include/linux/ssb/ssb.h
@@ -16,6 +16,12 @@ struct pcmcia_device;
struct ssb_bus;
struct ssb_driver;
+struct ssb_sprom_core_pwr_info {
+ u8 itssi_2g, itssi_5g;
+ u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
+ u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
+};
+
struct ssb_sprom {
u8 revision;
u8 il0mac[6]; /* MAC address for 802.11b/g */
@@ -26,9 +32,12 @@ struct ssb_sprom {
u8 et0mdcport; /* MDIO for enet0 */
u8 et1mdcport; /* MDIO for enet1 */
u16 board_rev; /* Board revision number from SPROM. */
+ u16 board_num; /* Board number from SPROM. */
+ u16 board_type; /* Board type from SPROM. */
u8 country_code; /* Country Code */
- u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
- u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
+ char alpha2[2]; /* Country Code as two chars like EU or US */
+ u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
+ u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
u16 pa0b0;
@@ -47,10 +56,10 @@ struct ssb_sprom {
u8 gpio1; /* GPIO pin 1 */
u8 gpio2; /* GPIO pin 2 */
u8 gpio3; /* GPIO pin 3 */
- u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
- u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
- u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
- u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
+ u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
+ u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
+ u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
+ u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
u8 itssi_a; /* Idle TSSI Target for A-PHY */
u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
u8 tri2g; /* 2.4GHz TX isolation */
@@ -61,8 +70,8 @@ struct ssb_sprom {
u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
- u8 rxpo2g; /* 2GHz RX power offset */
- u8 rxpo5g; /* 5GHz RX power offset */
+ s8 rxpo2g; /* 2GHz RX power offset */
+ s8 rxpo5g; /* 5GHz RX power offset */
u8 rssisav2g; /* 2GHz RSSI params */
u8 rssismc2g;
u8 rssismf2g;
@@ -82,16 +91,13 @@ struct ssb_sprom {
u16 boardflags2_hi; /* Board flags (bits 48-63) */
/* TODO store board flags in a single u64 */
+ struct ssb_sprom_core_pwr_info core_pwr_info[4];
+
/* Antenna gain values for up to 4 antennas
* on each band. Values in dBm/4 (Q5.2). Negative gain means the
* loss in the connectors is bigger than the gain. */
struct {
- struct {
- s8 a0, a1, a2, a3;
- } ghz24; /* 2.4GHz band */
- struct {
- s8 a0, a1, a2, a3;
- } ghz5; /* 5GHz band */
+ s8 a0, a1, a2, a3;
} antenna_gain;
struct {
@@ -103,14 +109,85 @@ struct ssb_sprom {
} ghz5;
} fem;
- /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
+ u16 mcs2gpo[8];
+ u16 mcs5gpo[8];
+ u16 mcs5glpo[8];
+ u16 mcs5ghpo[8];
+ u8 opo;
+
+ u8 rxgainerr2ga[3];
+ u8 rxgainerr5gla[3];
+ u8 rxgainerr5gma[3];
+ u8 rxgainerr5gha[3];
+ u8 rxgainerr5gua[3];
+
+ u8 noiselvl2ga[3];
+ u8 noiselvl5gla[3];
+ u8 noiselvl5gma[3];
+ u8 noiselvl5gha[3];
+ u8 noiselvl5gua[3];
+
+ u8 regrev;
+ u8 txchain;
+ u8 rxchain;
+ u8 antswitch;
+ u16 cddpo;
+ u16 stbcpo;
+ u16 bw40po;
+ u16 bwduppo;
+
+ u8 tempthresh;
+ u8 tempoffset;
+ u16 rawtempsense;
+ u8 measpower;
+ u8 tempsense_slope;
+ u8 tempcorrx;
+ u8 tempsense_option;
+ u8 freqoffset_corr;
+ u8 iqcal_swp_dis;
+ u8 hw_iqcal_en;
+ u8 elna2g;
+ u8 elna5g;
+ u8 phycal_tempdelta;
+ u8 temps_period;
+ u8 temps_hysteresis;
+ u8 measpower1;
+ u8 measpower2;
+ u8 pcieingress_war;
+
+ /* power per rate from sromrev 9 */
+ u16 cckbw202gpo;
+ u16 cckbw20ul2gpo;
+ u32 legofdmbw202gpo;
+ u32 legofdmbw20ul2gpo;
+ u32 legofdmbw205glpo;
+ u32 legofdmbw20ul5glpo;
+ u32 legofdmbw205gmpo;
+ u32 legofdmbw20ul5gmpo;
+ u32 legofdmbw205ghpo;
+ u32 legofdmbw20ul5ghpo;
+ u32 mcsbw202gpo;
+ u32 mcsbw20ul2gpo;
+ u32 mcsbw402gpo;
+ u32 mcsbw205glpo;
+ u32 mcsbw20ul5glpo;
+ u32 mcsbw405glpo;
+ u32 mcsbw205gmpo;
+ u32 mcsbw20ul5gmpo;
+ u32 mcsbw405gmpo;
+ u32 mcsbw205ghpo;
+ u32 mcsbw20ul5ghpo;
+ u32 mcsbw405ghpo;
+ u16 mcs32po;
+ u16 legofdm40duppo;
+ u8 sar2g;
+ u8 sar5g;
};
/* Information about the PCB the circuitry is soldered on. */
struct ssb_boardinfo {
u16 vendor;
u16 type;
- u8 rev;
};
@@ -166,6 +243,7 @@ struct ssb_bus_ops {
#define SSB_DEV_MINI_MACPHY 0x823
#define SSB_DEV_ARM_1176 0x824
#define SSB_DEV_ARM_7TDMI 0x825
+#define SSB_DEV_ARM_CM3 0x82A
/* Vendor-ID values */
#define SSB_VENDOR_BROADCOM 0x4243
--- a/include/linux/ssb/ssb_driver_gige.h
+++ b/include/linux/ssb/ssb_driver_gige.h
@@ -2,6 +2,7 @@
#define LINUX_SSB_DRIVER_GIGE_H_
#include <linux/ssb/ssb.h>
+#include <linux/bug.h>
#include <linux/pci.h>
#include <linux/spinlock.h>
--- a/include/linux/ssb/ssb_regs.h
+++ b/include/linux/ssb/ssb_regs.h
@@ -228,6 +228,7 @@
#define SSB_SPROM1_AGAIN_BG_SHIFT 0
#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
#define SSB_SPROM1_AGAIN_A_SHIFT 8
+#define SSB_SPROM1_CCODE 0x0076
/* SPROM Revision 2 (inherits from rev 1) */
#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
@@ -267,6 +268,7 @@
#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
/* SPROM Revision 4 */
+#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
@@ -389,6 +391,11 @@
#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
#define SSB_SPROM8_GPIOB_P3_SHIFT 8
+#define SSB_SPROM8_LEDDC 0x009A
+#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
+#define SSB_SPROM8_LEDDC_ON_SHIFT 8
+#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
+#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
@@ -404,6 +411,13 @@
#define SSB_SPROM8_AGAIN2_SHIFT 0
#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
#define SSB_SPROM8_AGAIN3_SHIFT 8
+#define SSB_SPROM8_TXRXC 0x00A2
+#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
+#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
+#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
+#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
+#define SSB_SPROM8_TXRXC_SWITCH 0xff00
+#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
#define SSB_SPROM8_RSSISMF2G 0x000F
#define SSB_SPROM8_RSSISMC2G 0x00F0
@@ -430,6 +444,7 @@
#define SSB_SPROM8_TRI5GH_SHIFT 8
#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
+#define SSB_SPROM8_RXPO2G_SHIFT 0
#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
#define SSB_SPROM8_RXPO5G_SHIFT 8
#define SSB_SPROM8_FEM2G 0x00AE
@@ -445,10 +460,71 @@
#define SSB_SROM8_FEM_ANTSWLUT 0xF800
#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
#define SSB_SPROM8_THERMAL 0x00B2
-#define SSB_SPROM8_MPWR_RAWTS 0x00B4
-#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
-#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
-#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
+#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
+#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
+#define SSB_SPROM8_THERMAL_TRESH 0xff00
+#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
+/* Temp sense related entries */
+#define SSB_SPROM8_RAWTS 0x00B4
+#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
+#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
+#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
+#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
+#define SSB_SPROM8_OPT_CORRX 0x00B6
+#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
+#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
+#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
+#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
+#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
+#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
+/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
+#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
+#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
+#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
+#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
+#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
+#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
+#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
+#define SSB_SPROM8_TEMPDELTA 0x00BA
+#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
+#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
+#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
+#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
+#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
+#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
+
+/* There are 4 blocks with power info sharing the same layout */
+#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
+#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
+#define SSB_SROM8_PWR_INFO_CORE2 0x0100
+#define SSB_SROM8_PWR_INFO_CORE3 0x0120
+
+#define SSB_SROM8_2G_MAXP_ITSSI 0x00
+#define SSB_SPROM8_2G_MAXP 0x00FF
+#define SSB_SPROM8_2G_ITSSI 0xFF00
+#define SSB_SPROM8_2G_ITSSI_SHIFT 8
+#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
+#define SSB_SROM8_2G_PA_1 0x04
+#define SSB_SROM8_2G_PA_2 0x06
+#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
+#define SSB_SPROM8_5G_MAXP 0x00FF
+#define SSB_SPROM8_5G_ITSSI 0xFF00
+#define SSB_SPROM8_5G_ITSSI_SHIFT 8
+#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
+#define SSB_SPROM8_5GH_MAXP 0x00FF
+#define SSB_SPROM8_5GL_MAXP 0xFF00
+#define SSB_SPROM8_5GL_MAXP_SHIFT 8
+#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
+#define SSB_SROM8_5G_PA_1 0x0E
+#define SSB_SROM8_5G_PA_2 0x10
+#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
+#define SSB_SROM8_5GL_PA_1 0x14
+#define SSB_SROM8_5GL_PA_2 0x16
+#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
+#define SSB_SROM8_5GH_PA_1 0x1A
+#define SSB_SROM8_5GH_PA_2 0x1C
+
+/* TODO: Make it deprecated */
#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
@@ -473,12 +549,23 @@
#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
#define SSB_SPROM8_PA1HIB1 0x00DA
#define SSB_SPROM8_PA1HIB2 0x00DC
+
#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
+#define SSB_SPROM8_2G_MCSPO 0x0152
+#define SSB_SPROM8_5G_MCSPO 0x0162
+#define SSB_SPROM8_5GL_MCSPO 0x0172
+#define SSB_SPROM8_5GH_MCSPO 0x0182
+
+#define SSB_SPROM8_CDDPO 0x0192
+#define SSB_SPROM8_STBCPO 0x0194
+#define SSB_SPROM8_BW40PO 0x0196
+#define SSB_SPROM8_BWDUPPO 0x0198
+
/* Values for boardflags_lo read from SPROM */
#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
Reference in New Issue View Git Blame Copy Permalink