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SBL will configure IPQ807x cores to boot at 800MHz as a safe default frequency that is provided by GPLL0, but GPLL0 is not currently configured as a possible parent in the APSS clock driver not being passed to it via DTS which will then cause the kernel to not properly identify the current CPU frequency during booting and will think that CPU is currently at XO frequency of 19.2MHz instead of 800MHz cores are actually at and print: cpufreq: cpufreq_online: CPU0: Running at unlisted initial frequency: 19200 KHz, changing to: 1017600 KHz So, lets import patches pending upstream to prevent GPLL scaling and feed the GPLL0 clock to APSS clock driver so we get: cpufreq: cpufreq_online: CPU0: Running at unlisted initial frequency: 800000 KHz, changing to: 1017600 KHz This is mostly cosmetic fix, but with all of the possible SBL and FW versions there could be edge cases resolved by this and not scaling GPLL-s anymore. Signed-off-by: Robert Marko <robimarko@gmail.com>
33 lines
1.3 KiB
Diff
33 lines
1.3 KiB
Diff
From 3b48a7d925a757b3fa53c04baaf68bb8313c3ffb Mon Sep 17 00:00:00 2001
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From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Date: Thu, 14 Sep 2023 12:29:58 +0530
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Subject: [PATCH] arm64: dts: qcom: ipq8074: include the GPLL0 as clock
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provider for mailbox
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While the kernel is booting up, APSS PLL will be running at 800MHz with
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GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
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configured to the rate based on the opp table and the source also will
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be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0,
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with this inclusion, CPU Freq correctly reports that CPU is running at
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800MHz rather than 24MHz.
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Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -920,8 +920,8 @@
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apcs_glb: mailbox@b111000 {
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compatible = "qcom,ipq8074-apcs-apps-global";
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reg = <0x0b111000 0x1000>;
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- clocks = <&a53pll>, <&xo>;
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- clock-names = "pll", "xo";
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+ clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
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+ clock-names = "pll", "xo", "gpll0";
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#clock-cells = <1>;
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#mbox-cells = <1>;
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