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The mt76x8 series SoCs use the MIPS generic systick timer. Sync the upstream Ralink systick driver changes and disable it for mt76x8 target to reduce the kernel size. Signed-off-by: Shiji Yang <yangshiji66@qq.com> Link: https://github.com/openwrt/openwrt/pull/16844 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
115 lines
3.0 KiB
Diff
115 lines
3.0 KiB
Diff
From: John Crispin <blogic@openwrt.org>
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Date: Sun, 14 Jul 2013 23:08:11 +0200
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Subject: [PATCH 1/2] MIPS: use set_mode() to enable/disable the cevt-r4k irq
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/kernel/cevt-r4k.c | 43 +++++++++++++++++++++++++++++++++++++
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drivers/clocksource/Kconfig | 5 +++++
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2 files changed, 48 insertions(+)
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--- a/arch/mips/kernel/cevt-r4k.c
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+++ b/arch/mips/kernel/cevt-r4k.c
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@@ -16,6 +16,31 @@
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#include <asm/time.h>
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#include <asm/cevt-r4k.h>
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+#ifdef CONFIG_CEVT_SYSTICK_QUIRK
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+static int mips_state_oneshot(struct clock_event_device *evt)
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+{
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+ unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
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+ if (!cp0_timer_irq_installed) {
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+ cp0_timer_irq_installed = 1;
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+ if (request_irq(evt->irq, c0_compare_interrupt, flags, "timer",
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+ c0_compare_interrupt))
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+ pr_err("Failed to request irq %d (timer)\n", evt->irq);
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+ }
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+
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+ return 0;
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+}
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+
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+static int mips_state_shutdown(struct clock_event_device *evt)
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+{
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+ if (cp0_timer_irq_installed) {
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+ cp0_timer_irq_installed = 0;
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+ free_irq(evt->irq, NULL);
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+ }
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+
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+ return 0;
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+}
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+#endif
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+
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static int mips_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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@@ -292,7 +317,9 @@ core_initcall(r4k_register_cpufreq_notif
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int r4k_clockevent_init(void)
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{
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+#ifndef CONFIG_CEVT_SYSTICK_QUIRK
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unsigned long flags = IRQF_PERCPU | IRQF_TIMER | IRQF_SHARED;
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+#endif
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd;
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unsigned int irq, min_delta;
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@@ -303,6 +330,15 @@ int r4k_clockevent_init(void)
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if (!c0_compare_int_usable())
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return -ENXIO;
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+#ifdef CONFIG_CEVT_SYSTICK_QUIRK
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+ /*
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+ * With vectored interrupts things are getting platform specific.
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+ * get_c0_compare_int is a hook to allow a platform to return the
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+ * interrupt number of its liking.
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+ */
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+ irq = get_c0_compare_int();
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+#endif
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+
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cd = &per_cpu(mips_clockevent_device, cpu);
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cd->name = "MIPS";
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@@ -314,11 +350,17 @@ int r4k_clockevent_init(void)
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cd->rating = 300;
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cd->cpumask = cpumask_of(cpu);
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+#ifdef CONFIG_CEVT_SYSTICK_QUIRK
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+ cd->irq = irq;
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+ cd->set_state_shutdown = mips_state_shutdown;
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+ cd->set_state_oneshot = mips_state_oneshot;
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+#endif
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cd->set_next_event = mips_next_event;
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cd->event_handler = mips_event_handler;
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clockevents_config_and_register(cd, mips_hpt_frequency, min_delta, 0x7fffffff);
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+#ifndef CONFIG_CEVT_SYSTICK_QUIRK
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if (cp0_timer_irq_installed)
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return 0;
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@@ -334,6 +376,7 @@ int r4k_clockevent_init(void)
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if (request_irq(irq, c0_compare_interrupt, flags, "timer",
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c0_compare_interrupt))
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pr_err("Failed to request irq %d (timer)\n", irq);
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+#endif
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return 0;
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}
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--- a/drivers/clocksource/Kconfig
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+++ b/drivers/clocksource/Kconfig
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@@ -731,10 +731,15 @@ config GOLDFISH_TIMER
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depends on RTC_DRV_GOLDFISH
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help
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Support for the timer/counter of goldfish-rtc
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+
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+config CEVT_SYSTICK_QUIRK
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+ bool
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+ default n
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config RALINK_TIMER
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bool "Ralink System Tick Counter"
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depends on SOC_RT305X || SOC_MT7620 || COMPILE_TEST
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+ select CEVT_SYSTICK_QUIRK
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select CLKSRC_MMIO
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select TIMER_OF
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help
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