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1d98363bd2
CI says that they need to be refreshed, so do so. Link: https://github.com/openwrt/openwrt/pull/16722 Signed-off-by: Robert Marko <robimarko@gmail.com>
62 lines
1.8 KiB
Diff
62 lines
1.8 KiB
Diff
From 2b88563ee5aafd9571d965b7f2093a0f58d98a31 Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Thu, 26 Nov 2020 12:02:21 +0100
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Subject: net: phy: EEE support for rtl838x
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* rename the target to realtek
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* add refactored DSA driver
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* add latest gpio driver
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* lots of arch cleanups
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* new irq driver
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* additional boards
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Submitted-by: Bert Vermeulen <bert@biot.com>
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Submitted-by: Birger Koblitz <mail@birger-koblitz.de>
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Submitted-by: Sander Vanheule <sander@svanheule.net>
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Submitted-by: Bjørn Mork <bjorn@mork.no>
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Submitted-by: John Crispin <john@phrozen.org>
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---
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drivers/net/phy/phylink. | 14 +++++++++++--
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1 file changed, 12 insertions(+), 2 deletions(-)
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--- a/drivers/net/phy/phylink.c
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+++ b/drivers/net/phy/phylink.c
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@@ -2503,6 +2503,11 @@ int phylink_ethtool_ksettings_set(struct
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* the presence of a PHY, this should not be changed as that
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* should be determined from the media side advertisement.
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*/
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+ if (pl->phydev->drv->get_port && pl->phydev->drv->set_port) {
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+ if(pl->phydev->drv->get_port(pl->phydev) != kset->base.port) {
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+ pl->phydev->drv->set_port(pl->phydev, kset->base.port);
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+ }
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+ }
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return phy_ethtool_ksettings_set(pl->phydev, &phy_kset);
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}
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@@ -2805,8 +2810,11 @@ int phylink_ethtool_get_eee(struct phyli
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ASSERT_RTNL();
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- if (pl->phydev)
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+ if (pl->phydev) {
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+ if (pl->phydev->drv->get_eee)
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+ return pl->phydev->drv->get_eee(pl->phydev, eee);
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ret = phy_ethtool_get_eee(pl->phydev, eee);
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+ }
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return ret;
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}
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@@ -2823,8 +2831,11 @@ int phylink_ethtool_set_eee(struct phyli
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ASSERT_RTNL();
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- if (pl->phydev)
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+ if (pl->phydev) {
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+ if (pl->phydev->drv->set_eee)
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+ return pl->phydev->drv->set_eee(pl->phydev, eee);
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ret = phy_ethtool_set_eee(pl->phydev, eee);
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+ }
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return ret;
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}
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