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f2f42a54e8
The qca8k patch series brings the numbering to 799. This patch renames 7xx patches to create space for more backports to be added. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> [rename 729->719] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
131 lines
4.8 KiB
Diff
131 lines
4.8 KiB
Diff
From 83a3ceb39b2495171aabe9446271b94c678354f3 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Fri, 14 May 2021 23:00:01 +0200
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Subject: [PATCH] net: dsa: qca8k: add priority tweak to qca8337 switch
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The port 5 of the qca8337 have some problem in flood condition. The
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original legacy driver had some specific buffer and priority settings
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for the different port suggested by the QCA switch team. Add this
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missing settings to improve switch stability under load condition.
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The packet priority tweak is only needed for the qca8337 switch and
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other qca8k switch are not affected.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/qca8k.c | 47 +++++++++++++++++++++++++++++++++++++++++
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drivers/net/dsa/qca8k.h | 25 ++++++++++++++++++++++
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2 files changed, 72 insertions(+)
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--- a/drivers/net/dsa/qca8k.c
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+++ b/drivers/net/dsa/qca8k.c
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@@ -779,6 +779,7 @@ qca8k_setup(struct dsa_switch *ds)
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{
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struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
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int ret, i;
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+ u32 mask;
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/* Make sure that port 0 is the cpu port */
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if (!dsa_is_cpu_port(ds, 0)) {
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@@ -884,6 +885,51 @@ qca8k_setup(struct dsa_switch *ds)
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}
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}
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+ /* The port 5 of the qca8337 have some problem in flood condition. The
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+ * original legacy driver had some specific buffer and priority settings
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+ * for the different port suggested by the QCA switch team. Add this
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+ * missing settings to improve switch stability under load condition.
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+ * This problem is limited to qca8337 and other qca8k switch are not affected.
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+ */
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+ if (priv->switch_id == QCA8K_ID_QCA8337) {
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+ for (i = 0; i < QCA8K_NUM_PORTS; i++) {
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+ switch (i) {
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+ /* The 2 CPU port and port 5 requires some different
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+ * priority than any other ports.
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+ */
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+ case 0:
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+ case 5:
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+ case 6:
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+ mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x4) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x4) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI4(0x6) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI5(0x8) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PORT(0x1e);
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+ break;
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+ default:
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+ mask = QCA8K_PORT_HOL_CTRL0_EG_PRI0(0x3) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI1(0x4) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI2(0x6) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PRI3(0x8) |
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+ QCA8K_PORT_HOL_CTRL0_EG_PORT(0x19);
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+ }
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+ qca8k_write(priv, QCA8K_REG_PORT_HOL_CTRL0(i), mask);
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+
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+ mask = QCA8K_PORT_HOL_CTRL1_ING(0x6) |
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+ QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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+ QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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+ QCA8K_PORT_HOL_CTRL1_WRED_EN;
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+ qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
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+ QCA8K_PORT_HOL_CTRL1_ING_BUF |
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+ QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
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+ QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
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+ QCA8K_PORT_HOL_CTRL1_WRED_EN,
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+ mask);
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+ }
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+ }
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+
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/* Setup our port MTUs to match power on defaults */
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for (i = 0; i < QCA8K_NUM_PORTS; i++)
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priv->port_mtu[i] = ETH_FRAME_LEN + ETH_FCS_LEN;
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@@ -1578,6 +1624,7 @@ qca8k_sw_probe(struct mdio_device *mdiod
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return -ENODEV;
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}
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+ priv->switch_id = id;
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priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
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if (!priv->ds)
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return -ENOMEM;
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--- a/drivers/net/dsa/qca8k.h
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+++ b/drivers/net/dsa/qca8k.h
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@@ -168,6 +168,30 @@
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#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
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#define QCA8K_PORT_LOOKUP_LEARN BIT(20)
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+#define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24)
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+#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24)
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+
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+#define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
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+#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
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+#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
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+#define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
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+#define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
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+#define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
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+#define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
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+
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/* Pkt edit registers */
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#define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
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@@ -220,6 +244,7 @@ struct qca8k_match_data {
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};
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struct qca8k_priv {
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+ u8 switch_id;
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struct regmap *regmap;
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struct mii_bus *bus;
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struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
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