mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-28 09:39:00 +00:00
4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
32 lines
992 B
Diff
32 lines
992 B
Diff
From b085b6233065b1e5145fbf93d75264b2042c0eb5 Mon Sep 17 00:00:00 2001
|
|
From: Xingyu Wu <xingyu.wu@starfivetech.com>
|
|
Date: Tue, 14 Mar 2023 21:24:37 +0800
|
|
Subject: [PATCH 106/122] riscv: dts: starfive: jh7100: Add watchdog node
|
|
|
|
Add watchdog node for the StarFive JH7100 RISC-V SoC.
|
|
|
|
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
|
|
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
|
|
---
|
|
arch/riscv/boot/dts/starfive/jh7100.dtsi | 10 ++++++++++
|
|
1 file changed, 10 insertions(+)
|
|
|
|
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
|
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
|
|
@@ -238,5 +238,15 @@
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
+
|
|
+ watchdog@12480000 {
|
|
+ compatible = "starfive,jh7100-wdt";
|
|
+ reg = <0x0 0x12480000 0x0 0x10000>;
|
|
+ clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
|
|
+ <&clkgen JH7100_CLK_WDT_CORE>;
|
|
+ clock-names = "apb", "core";
|
|
+ resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
|
|
+ <&rstgen JH7100_RSTN_WDT>;
|
|
+ };
|
|
};
|
|
};
|