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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
136 lines
3.7 KiB
Diff
136 lines
3.7 KiB
Diff
From 6a2392c96041d0599d33799a9aedbcdbfb4030b6 Mon Sep 17 00:00:00 2001
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From: Minda Chen <minda.chen@starfivetech.com>
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Date: Thu, 18 May 2023 19:27:48 +0800
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Subject: [PATCH 091/122] dt-bindings: usb: Add StarFive JH7110 USB controller
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StarFive JH7110 platforms USB have a wrapper module around
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the Cadence USBSS-DRD controller. Add binding information doc
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for that.
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Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
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Reviewed-by: Peter Chen <peter.chen@kernel.org>
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Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
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---
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.../bindings/usb/starfive,jh7110-usb.yaml | 115 ++++++++++++++++++
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1 file changed, 115 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
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@@ -0,0 +1,115 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
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+
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+maintainers:
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+ - Minda Chen <minda.chen@starfivetech.com>
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+
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+properties:
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+ compatible:
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+ const: starfive,jh7110-usb
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+
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+ ranges: true
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+
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+ starfive,stg-syscon:
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+ $ref: /schemas/types.yaml#/definitions/phandle-array
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+ items:
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+ - items:
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+ - description: phandle to System Register Controller stg_syscon node.
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+ - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB.
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+ description:
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+ The phandle to System Register Controller syscon node and the offset
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+ of STG_SYSCONSAIF__SYSCFG register for USB.
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+
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+ dr_mode:
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+ enum: [host, otg, peripheral]
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+
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+ "#address-cells":
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+ enum: [1, 2]
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+
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+ "#size-cells":
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+ enum: [1, 2]
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+
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+ clocks:
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+ items:
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+ - description: link power management clock
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+ - description: standby clock
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+ - description: APB clock
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+ - description: AXI clock
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+ - description: UTMI APB clock
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+
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+ clock-names:
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+ items:
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+ - const: lpm
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+ - const: stb
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+ - const: apb
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+ - const: axi
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+ - const: utmi_apb
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+
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+ resets:
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+ items:
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+ - description: Power up reset
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+ - description: APB clock reset
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+ - description: AXI clock reset
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+ - description: UTMI APB clock reset
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+
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+ reset-names:
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+ items:
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+ - const: pwrup
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+ - const: apb
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+ - const: axi
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+ - const: utmi_apb
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+
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+patternProperties:
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+ "^usb@[0-9a-f]+$":
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+ $ref: cdns,usb3.yaml#
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+ description: Required child node
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+
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+required:
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+ - compatible
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+ - ranges
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+ - starfive,stg-syscon
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+ - '#address-cells'
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+ - '#size-cells'
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+ - dr_mode
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+ - clocks
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+ - resets
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ usb@10100000 {
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+ compatible = "starfive,jh7110-usb";
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+ ranges = <0x0 0x10100000 0x100000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ starfive,stg-syscon = <&stg_syscon 0x4>;
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+ clocks = <&syscrg 4>,
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+ <&stgcrg 5>,
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+ <&stgcrg 1>,
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+ <&stgcrg 3>,
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+ <&stgcrg 2>;
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+ clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
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+ resets = <&stgcrg 10>,
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+ <&stgcrg 8>,
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+ <&stgcrg 7>,
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+ <&stgcrg 9>;
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+ reset-names = "pwrup", "apb", "axi", "utmi_apb";
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+ dr_mode = "host";
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+
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+ usb@0 {
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+ compatible = "cdns,usb3";
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+ reg = <0x0 0x10000>,
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+ <0x10000 0x10000>,
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+ <0x20000 0x10000>;
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+ reg-names = "otg", "xhci", "dev";
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+ interrupts = <100>, <108>, <110>;
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+ interrupt-names = "host", "peripheral", "otg";
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+ maximum-speed = "super-speed";
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+ };
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+ };
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