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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
147 lines
5.2 KiB
Diff
147 lines
5.2 KiB
Diff
From 365bb978e5e11a16c362d9c2c64d7bf8d04999df Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 1 Apr 2023 19:19:24 +0800
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Subject: [PATCH 012/122] reset: starfive: jh71x0: Use 32bit I/O on 32bit
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registers
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We currently use 64bit I/O on the 32bit registers. This works because
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there are an even number of assert and status registers, so they're only
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ever accessed in pairs on 64bit boundaries.
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There are however other reset controllers for audio and video on the
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JH7100 SoC with only one status register that isn't 64bit aligned so
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64bit I/O results in an unaligned access exception.
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Switch to 32bit I/O in preparation for supporting these resets too.
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Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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.../reset/starfive/reset-starfive-jh7100.c | 14 ++++-----
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.../reset/starfive/reset-starfive-jh71x0.c | 31 +++++++++----------
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.../reset/starfive/reset-starfive-jh71x0.h | 2 +-
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3 files changed, 23 insertions(+), 24 deletions(-)
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--- a/drivers/reset/starfive/reset-starfive-jh7100.c
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+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
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@@ -30,16 +30,16 @@
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* lines don't though, so store the expected value of the status registers when
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* all lines are asserted.
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*/
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-static const u64 jh7100_reset_asserted[2] = {
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+static const u32 jh7100_reset_asserted[4] = {
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/* STATUS0 */
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- BIT_ULL_MASK(JH7100_RST_U74) |
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- BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
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- BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
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+ BIT(JH7100_RST_U74 % 32) |
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+ BIT(JH7100_RST_VP6_DRESET % 32) |
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+ BIT(JH7100_RST_VP6_BRESET % 32),
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/* STATUS1 */
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- BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
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- BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
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+ BIT(JH7100_RST_HIFI4_DRESET % 32) |
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+ BIT(JH7100_RST_HIFI4_BRESET % 32),
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/* STATUS2 */
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- BIT_ULL_MASK(JH7100_RST_E24) |
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+ BIT(JH7100_RST_E24 % 32),
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/* STATUS3 */
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0,
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};
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--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
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+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
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@@ -8,7 +8,6 @@
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#include <linux/bitmap.h>
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#include <linux/device.h>
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#include <linux/io.h>
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-#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/iopoll.h>
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#include <linux/reset-controller.h>
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#include <linux/spinlock.h>
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@@ -21,7 +20,7 @@ struct jh71x0_reset {
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spinlock_t lock;
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void __iomem *assert;
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void __iomem *status;
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- const u64 *asserted;
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+ const u32 *asserted;
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};
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static inline struct jh71x0_reset *
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@@ -34,12 +33,12 @@ static int jh71x0_reset_update(struct re
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unsigned long id, bool assert)
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{
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struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
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- unsigned long offset = BIT_ULL_WORD(id);
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- u64 mask = BIT_ULL_MASK(id);
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- void __iomem *reg_assert = data->assert + offset * sizeof(u64);
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- void __iomem *reg_status = data->status + offset * sizeof(u64);
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- u64 done = data->asserted ? data->asserted[offset] & mask : 0;
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- u64 value;
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+ unsigned long offset = id / 32;
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+ u32 mask = BIT(id % 32);
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+ void __iomem *reg_assert = data->assert + offset * sizeof(u32);
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+ void __iomem *reg_status = data->status + offset * sizeof(u32);
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+ u32 done = data->asserted ? data->asserted[offset] & mask : 0;
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+ u32 value;
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unsigned long flags;
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int ret;
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@@ -48,15 +47,15 @@ static int jh71x0_reset_update(struct re
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spin_lock_irqsave(&data->lock, flags);
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- value = readq(reg_assert);
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+ value = readl(reg_assert);
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if (assert)
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value |= mask;
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else
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value &= ~mask;
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- writeq(value, reg_assert);
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+ writel(value, reg_assert);
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/* if the associated clock is gated, deasserting might otherwise hang forever */
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- ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
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+ ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
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spin_unlock_irqrestore(&data->lock, flags);
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return ret;
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@@ -90,10 +89,10 @@ static int jh71x0_reset_status(struct re
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unsigned long id)
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{
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struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
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- unsigned long offset = BIT_ULL_WORD(id);
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- u64 mask = BIT_ULL_MASK(id);
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- void __iomem *reg_status = data->status + offset * sizeof(u64);
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- u64 value = readq(reg_status);
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+ unsigned long offset = id / 32;
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+ u32 mask = BIT(id % 32);
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+ void __iomem *reg_status = data->status + offset * sizeof(u32);
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+ u32 value = readl(reg_status);
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return !((value ^ data->asserted[offset]) & mask);
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}
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@@ -107,7 +106,7 @@ static const struct reset_control_ops jh
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int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
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void __iomem *assert, void __iomem *status,
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- const u64 *asserted, unsigned int nr_resets,
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+ const u32 *asserted, unsigned int nr_resets,
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struct module *owner)
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{
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struct jh71x0_reset *data;
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--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
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+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
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@@ -8,7 +8,7 @@
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int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
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void __iomem *assert, void __iomem *status,
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- const u64 *asserted, unsigned int nr_resets,
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+ const u32 *asserted, unsigned int nr_resets,
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struct module *owner);
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#endif /* __RESET_STARFIVE_JH71X0_H */
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