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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
291 lines
8.3 KiB
Diff
291 lines
8.3 KiB
Diff
From 8daa4c812f3b32a4d56ab48945e552a137fca9b7 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 1 Apr 2023 19:19:17 +0800
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Subject: [PATCH 005/122] clk: starfive: Rename clk-starfive-jh7100.h to
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clk-starfive-jh71x0.h
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Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h for making
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the code to be common.
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Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
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---
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drivers/clk/starfive/clk-starfive-jh7100-audio.c | 2 +-
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drivers/clk/starfive/clk-starfive-jh7100.c | 2 +-
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drivers/clk/starfive/clk-starfive-jh71x0.c | 2 +-
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.../starfive/{clk-starfive-jh7100.h => clk-starfive-jh71x0.h} | 0
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4 files changed, 3 insertions(+), 3 deletions(-)
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rename drivers/clk/starfive/{clk-starfive-jh7100.h => clk-starfive-jh71x0.h} (100%)
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--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
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+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
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@@ -16,7 +16,7 @@
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#include <dt-bindings/clock/starfive-jh7100-audio.h>
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-#include "clk-starfive-jh7100.h"
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+#include "clk-starfive-jh71x0.h"
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/* external clocks */
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#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
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--- a/drivers/clk/starfive/clk-starfive-jh7100.c
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+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
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@@ -15,7 +15,7 @@
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#include <dt-bindings/clock/starfive-jh7100.h>
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-#include "clk-starfive-jh7100.h"
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+#include "clk-starfive-jh71x0.h"
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/* external clocks */
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#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
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--- a/drivers/clk/starfive/clk-starfive-jh71x0.c
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+++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
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@@ -10,7 +10,7 @@
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#include <linux/device.h>
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#include <linux/io.h>
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-#include "clk-starfive-jh7100.h"
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+#include "clk-starfive-jh71x0.h"
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static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
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{
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--- a/drivers/clk/starfive/clk-starfive-jh7100.h
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+++ /dev/null
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@@ -1,114 +0,0 @@
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-/* SPDX-License-Identifier: GPL-2.0 */
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-#ifndef __CLK_STARFIVE_JH7100_H
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-#define __CLK_STARFIVE_JH7100_H
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-
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-#include <linux/bits.h>
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-#include <linux/clk-provider.h>
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-#include <linux/device.h>
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-#include <linux/spinlock.h>
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-
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-/* register fields */
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-#define JH7100_CLK_ENABLE BIT(31)
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-#define JH7100_CLK_INVERT BIT(30)
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-#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
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-#define JH7100_CLK_MUX_SHIFT 24
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-#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
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-#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
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-#define JH7100_CLK_FRAC_SHIFT 8
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-#define JH7100_CLK_INT_MASK GENMASK(7, 0)
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-
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-/* fractional divider min/max */
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-#define JH7100_CLK_FRAC_MIN 100UL
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-#define JH7100_CLK_FRAC_MAX 25599UL
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-
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-/* clock data */
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-struct jh7100_clk_data {
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- const char *name;
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- unsigned long flags;
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- u32 max;
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- u8 parents[4];
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-};
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-
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-#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
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- .name = _name, \
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- .flags = CLK_SET_RATE_PARENT | (_flags), \
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- .max = JH7100_CLK_ENABLE, \
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- .parents = { [0] = _parent }, \
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-}
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-
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-#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
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- .name = _name, \
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- .flags = 0, \
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- .max = _max, \
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- .parents = { [0] = _parent }, \
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-}
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-
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-#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
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- .name = _name, \
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- .flags = _flags, \
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- .max = JH7100_CLK_ENABLE | (_max), \
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- .parents = { [0] = _parent }, \
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-}
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-
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-#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
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- .name = _name, \
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- .flags = 0, \
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- .max = JH7100_CLK_FRAC_MAX, \
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- .parents = { [0] = _parent }, \
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-}
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-
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-#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
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- .name = _name, \
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- .flags = 0, \
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- .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
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- .parents = { __VA_ARGS__ }, \
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-}
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-
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-#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
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- .name = _name, \
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- .flags = _flags, \
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- .max = JH7100_CLK_ENABLE | \
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- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
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- .parents = { __VA_ARGS__ }, \
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-}
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-
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-#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
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- .name = _name, \
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- .flags = 0, \
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- .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
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- .parents = { __VA_ARGS__ }, \
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-}
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-
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-#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
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- .name = _name, \
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- .flags = _flags, \
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- .max = JH7100_CLK_ENABLE | \
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- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
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- .parents = { __VA_ARGS__ }, \
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-}
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-
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-#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
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- .name = _name, \
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- .flags = CLK_SET_RATE_PARENT, \
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- .max = JH7100_CLK_INVERT, \
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- .parents = { [0] = _parent }, \
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-}
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-
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-struct jh7100_clk {
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- struct clk_hw hw;
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- unsigned int idx;
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- unsigned int max_div;
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-};
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-
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-struct jh7100_clk_priv {
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- /* protect clk enable and set rate/parent from happening at the same time */
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- spinlock_t rmw_lock;
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- struct device *dev;
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- void __iomem *base;
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- struct clk_hw *pll[3];
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- struct jh7100_clk reg[];
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-};
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-
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-const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
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-
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-#endif
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--- /dev/null
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+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
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@@ -0,0 +1,114 @@
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+/* SPDX-License-Identifier: GPL-2.0 */
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+#ifndef __CLK_STARFIVE_JH7100_H
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+#define __CLK_STARFIVE_JH7100_H
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+
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+#include <linux/bits.h>
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+#include <linux/clk-provider.h>
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+#include <linux/device.h>
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+#include <linux/spinlock.h>
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+
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+/* register fields */
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+#define JH7100_CLK_ENABLE BIT(31)
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+#define JH7100_CLK_INVERT BIT(30)
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+#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
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+#define JH7100_CLK_MUX_SHIFT 24
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+#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
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+#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
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+#define JH7100_CLK_FRAC_SHIFT 8
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+#define JH7100_CLK_INT_MASK GENMASK(7, 0)
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+
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+/* fractional divider min/max */
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+#define JH7100_CLK_FRAC_MIN 100UL
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+#define JH7100_CLK_FRAC_MAX 25599UL
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+
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+/* clock data */
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+struct jh7100_clk_data {
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+ const char *name;
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+ unsigned long flags;
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+ u32 max;
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+ u8 parents[4];
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+};
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+
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+#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
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+ .name = _name, \
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+ .flags = CLK_SET_RATE_PARENT | (_flags), \
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+ .max = JH7100_CLK_ENABLE, \
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+ .parents = { [0] = _parent }, \
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+}
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+
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+#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
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+ .name = _name, \
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+ .flags = 0, \
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+ .max = _max, \
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+ .parents = { [0] = _parent }, \
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+}
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+
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+#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
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+ .name = _name, \
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+ .flags = _flags, \
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+ .max = JH7100_CLK_ENABLE | (_max), \
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+ .parents = { [0] = _parent }, \
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+}
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+
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+#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
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+ .name = _name, \
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+ .flags = 0, \
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+ .max = JH7100_CLK_FRAC_MAX, \
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+ .parents = { [0] = _parent }, \
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+}
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+
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+#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
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+ .name = _name, \
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+ .flags = 0, \
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+ .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
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+ .parents = { __VA_ARGS__ }, \
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+}
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+
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+#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
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+ .name = _name, \
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+ .flags = _flags, \
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+ .max = JH7100_CLK_ENABLE | \
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+ (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
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+ .parents = { __VA_ARGS__ }, \
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+}
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+
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+#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
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+ .name = _name, \
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+ .flags = 0, \
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+ .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
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+ .parents = { __VA_ARGS__ }, \
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+}
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+
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+#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
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+ .name = _name, \
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+ .flags = _flags, \
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+ .max = JH7100_CLK_ENABLE | \
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+ (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
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+ .parents = { __VA_ARGS__ }, \
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+}
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+
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+#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
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+ .name = _name, \
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+ .flags = CLK_SET_RATE_PARENT, \
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+ .max = JH7100_CLK_INVERT, \
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+ .parents = { [0] = _parent }, \
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+}
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+
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+struct jh7100_clk {
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+ struct clk_hw hw;
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+ unsigned int idx;
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+ unsigned int max_div;
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+};
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+
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+struct jh7100_clk_priv {
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+ /* protect clk enable and set rate/parent from happening at the same time */
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+ spinlock_t rmw_lock;
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+ struct device *dev;
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+ void __iomem *base;
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+ struct clk_hw *pll[3];
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+ struct jh7100_clk reg[];
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+};
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+
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+const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
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+
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+#endif
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