mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-28 09:39:00 +00:00
f038c0c18f
Drop redundant label with new LED color/function format declared. This was needed previously when the new format wasn't supported by leds.sh functions script. Now that is supported this property can be removed in favor of the new format. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
379 lines
7.9 KiB
Plaintext
379 lines
7.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "rtl839x.dtsi"
|
|
#include "rtl83xx_panasonic_mxxeg-pn28xx0k.dtsi"
|
|
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
|
|
/ {
|
|
compatible = "panasonic,m48eg-pn28480k", "realtek,rtl8393-soc";
|
|
model = "Panasonic Switch-M48eG PN28480K";
|
|
|
|
aliases {
|
|
led-boot = &led_status_eco_green;
|
|
led-failsafe = &led_status_eco_amber;
|
|
led-running = &led_status_eco_green;
|
|
led-upgrade = &led_status_eco_green;
|
|
};
|
|
|
|
fan: gpio-fan {
|
|
compatible = "gpio-fan";
|
|
gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
|
|
/* the actual speeds (rpm) are unknown, just use dummy values */
|
|
gpio-fan,speed-map = <1 0>, <2 1>;
|
|
#cooling-cells = <2>;
|
|
};
|
|
|
|
/*
|
|
* sfp0/1/2/3 are "combo" port with each TP port (45/46/47/48),
|
|
* and they are connected to the RTL8218FB. Currently, there is
|
|
* no support for the chip and only TP ports work by the RTL8218B
|
|
* support.
|
|
*/
|
|
sfp0: sfp-p45 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c0>;
|
|
tx-fault-gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
|
|
tx-disable-gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
|
|
los-gpio = <&gpio1 3 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
sfp1: sfp-p46 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c1>;
|
|
tx-fault-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
|
tx-disable-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
|
|
los-gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
sfp2: sfp-p47 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c2>;
|
|
tx-fault-gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
|
|
tx-disable-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpio = <&gpio1 10 GPIO_ACTIVE_LOW>;
|
|
los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
sfp3: sfp-p48 {
|
|
compatible = "sff,sfp";
|
|
i2c-bus = <&i2c3>;
|
|
tx-fault-gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
|
tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
|
mod-def0-gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
|
|
los-gpio = <&gpio1 15 GPIO_ACTIVE_HIGH>;
|
|
};
|
|
|
|
thermal-zones {
|
|
/*
|
|
* Zone for SoC temperature
|
|
*
|
|
* Fan speed:
|
|
*
|
|
* - 0-44 celsius: Low
|
|
* - 45-54 celsius: High
|
|
*/
|
|
cpu-thermal {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <2000>;
|
|
|
|
thermal-sensors = <&tsens_soc>;
|
|
|
|
trips {
|
|
cpu_alert: trip-point {
|
|
temperature = <45000>;
|
|
hysteresis = <4000>;
|
|
type = "active";
|
|
};
|
|
|
|
cpu_crit {
|
|
temperature = <55000>;
|
|
hysteresis = <1000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map {
|
|
trip = <&cpu_alert>;
|
|
cooling-device = <&fan 0 1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
* Zone for system temperature
|
|
*
|
|
* Fan speed:
|
|
*
|
|
* - 0-39 celsius: Low
|
|
* - 40-49 celsius: High
|
|
*
|
|
* Note: official recommended ranges of temperature on each
|
|
* fan speed setting:
|
|
*
|
|
* - Low speed : 0-40 celsius
|
|
* - High speed: 0-50 celsius
|
|
*
|
|
* (stock firmware doesn't support auto-selection of
|
|
* speed and need to be selected manually by user)
|
|
*/
|
|
sys-thermal {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <2000>;
|
|
|
|
thermal-sensors = <&tsens_sys>;
|
|
|
|
trips {
|
|
sys_alert: trip-point {
|
|
temperature = <40000>;
|
|
hysteresis = <4000>;
|
|
type = "active";
|
|
};
|
|
|
|
sys_crit {
|
|
temperature = <50000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map {
|
|
trip = <&sys_alert>;
|
|
cooling-device = <&fan 0 1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&leds {
|
|
led_status_eco_amber: led-5 {
|
|
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
|
color = <LED_COLOR_ID_AMBER>;
|
|
function = LED_FUNCTION_STATUS;
|
|
function-enumerator = <1>;
|
|
};
|
|
|
|
led_status_eco_green: led-6 {
|
|
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
|
|
color = <LED_COLOR_ID_GREEN>;
|
|
function = LED_FUNCTION_STATUS;
|
|
function-enumerator = <2>;
|
|
};
|
|
};
|
|
|
|
&i2c_gpio_0 {
|
|
scl-gpios = <&gpio0 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio0 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
|
|
/* Microchip TCN75A (for SoC) */
|
|
tsens_soc: sensor@48 {
|
|
compatible = "microchip,tcn75";
|
|
reg = <0x48>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
/* Microchip TCN75A (for System) */
|
|
tsens_sys: sensor@49 {
|
|
compatible = "microchip,tcn75";
|
|
reg = <0x49>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
};
|
|
|
|
&i2c_gpio_1 {
|
|
scl-gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
sda-gpios = <&gpio0 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
|
|
};
|
|
|
|
&gpio2 {
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&gpio0>;
|
|
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
|
|
|
/*
|
|
* GPIO12 (IO1_4): 5x RTL8218B + RTL8218FB
|
|
*
|
|
* This GPIO pin should be specified as "reset-gpio" in mdio node,
|
|
* but the current configuration of RTL8218B phy in the phy driver
|
|
* seems to be incomplete and RTL8218FB phy won't be configured on
|
|
* RTL8218D support. So, ethernet ports on these phys will be broken
|
|
* after hard-resetting.
|
|
* (RTL8218FB phy will be detected as RTL8218D by the phy driver)
|
|
* At the moment, configure this GPIO pin as gpio-hog to avoid breaking
|
|
* by resetting.
|
|
*/
|
|
ext_switch_reset {
|
|
gpio-hog;
|
|
gpios = <12 GPIO_ACTIVE_HIGH>;
|
|
output-high;
|
|
line-name = "ext-switch-reset";
|
|
};
|
|
};
|
|
|
|
&i2c_switch {
|
|
i2c0: i2c@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0>;
|
|
};
|
|
|
|
i2c1: i2c@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
};
|
|
|
|
i2c2: i2c@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
};
|
|
|
|
i2c3: i2c@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
ðernet0 {
|
|
mdio-bus {
|
|
compatible = "realtek,rtl838x-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
EXTERNAL_PHY(0)
|
|
EXTERNAL_PHY(1)
|
|
EXTERNAL_PHY(2)
|
|
EXTERNAL_PHY(3)
|
|
EXTERNAL_PHY(4)
|
|
EXTERNAL_PHY(5)
|
|
EXTERNAL_PHY(6)
|
|
EXTERNAL_PHY(7)
|
|
|
|
EXTERNAL_PHY(8)
|
|
EXTERNAL_PHY(9)
|
|
EXTERNAL_PHY(10)
|
|
EXTERNAL_PHY(11)
|
|
EXTERNAL_PHY(12)
|
|
EXTERNAL_PHY(13)
|
|
EXTERNAL_PHY(14)
|
|
EXTERNAL_PHY(15)
|
|
|
|
EXTERNAL_PHY(16)
|
|
EXTERNAL_PHY(17)
|
|
EXTERNAL_PHY(18)
|
|
EXTERNAL_PHY(19)
|
|
EXTERNAL_PHY(20)
|
|
EXTERNAL_PHY(21)
|
|
EXTERNAL_PHY(22)
|
|
EXTERNAL_PHY(23)
|
|
|
|
EXTERNAL_PHY(24)
|
|
EXTERNAL_PHY(25)
|
|
EXTERNAL_PHY(26)
|
|
EXTERNAL_PHY(27)
|
|
EXTERNAL_PHY(28)
|
|
EXTERNAL_PHY(29)
|
|
EXTERNAL_PHY(30)
|
|
EXTERNAL_PHY(31)
|
|
|
|
EXTERNAL_PHY(32)
|
|
EXTERNAL_PHY(33)
|
|
EXTERNAL_PHY(34)
|
|
EXTERNAL_PHY(35)
|
|
EXTERNAL_PHY(36)
|
|
EXTERNAL_PHY(37)
|
|
EXTERNAL_PHY(38)
|
|
EXTERNAL_PHY(39)
|
|
|
|
/* RTL8218FB */
|
|
EXTERNAL_PHY(40)
|
|
EXTERNAL_PHY(41)
|
|
EXTERNAL_PHY(42)
|
|
EXTERNAL_PHY(43)
|
|
EXTERNAL_PHY(44)
|
|
EXTERNAL_PHY(45)
|
|
EXTERNAL_PHY(46)
|
|
EXTERNAL_PHY(47)
|
|
};
|
|
};
|
|
|
|
&switch0 {
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
SWITCH_PORT(0, 1, qsgmii)
|
|
SWITCH_PORT(1, 2, qsgmii)
|
|
SWITCH_PORT(2, 3, qsgmii)
|
|
SWITCH_PORT(3, 4, qsgmii)
|
|
SWITCH_PORT(4, 5, qsgmii)
|
|
SWITCH_PORT(5, 6, qsgmii)
|
|
SWITCH_PORT(6, 7, qsgmii)
|
|
SWITCH_PORT(7, 8, qsgmii)
|
|
|
|
SWITCH_PORT(8, 9, qsgmii)
|
|
SWITCH_PORT(9, 10, qsgmii)
|
|
SWITCH_PORT(10, 11, qsgmii)
|
|
SWITCH_PORT(11, 12, qsgmii)
|
|
SWITCH_PORT(12, 13, qsgmii)
|
|
SWITCH_PORT(13, 14, qsgmii)
|
|
SWITCH_PORT(14, 15, qsgmii)
|
|
SWITCH_PORT(15, 16, qsgmii)
|
|
|
|
SWITCH_PORT(16, 17, qsgmii)
|
|
SWITCH_PORT(17, 18, qsgmii)
|
|
SWITCH_PORT(18, 19, qsgmii)
|
|
SWITCH_PORT(19, 20, qsgmii)
|
|
SWITCH_PORT(20, 21, qsgmii)
|
|
SWITCH_PORT(21, 22, qsgmii)
|
|
SWITCH_PORT(22, 23, qsgmii)
|
|
SWITCH_PORT(23, 24, qsgmii)
|
|
|
|
SWITCH_PORT(24, 25, qsgmii)
|
|
SWITCH_PORT(25, 26, qsgmii)
|
|
SWITCH_PORT(26, 27, qsgmii)
|
|
SWITCH_PORT(27, 28, qsgmii)
|
|
SWITCH_PORT(28, 29, qsgmii)
|
|
SWITCH_PORT(29, 30, qsgmii)
|
|
SWITCH_PORT(30, 31, qsgmii)
|
|
SWITCH_PORT(31, 32, qsgmii)
|
|
|
|
SWITCH_PORT(32, 33, qsgmii)
|
|
SWITCH_PORT(33, 34, qsgmii)
|
|
SWITCH_PORT(34, 35, qsgmii)
|
|
SWITCH_PORT(35, 36, qsgmii)
|
|
SWITCH_PORT(36, 37, qsgmii)
|
|
SWITCH_PORT(37, 38, qsgmii)
|
|
SWITCH_PORT(38, 39, qsgmii)
|
|
SWITCH_PORT(39, 40, qsgmii)
|
|
|
|
SWITCH_PORT(40, 41, qsgmii)
|
|
SWITCH_PORT(41, 42, qsgmii)
|
|
SWITCH_PORT(42, 43, qsgmii)
|
|
SWITCH_PORT(43, 44, qsgmii)
|
|
SWITCH_PORT(44, 45, qsgmii)
|
|
SWITCH_PORT(45, 46, qsgmii)
|
|
SWITCH_PORT(46, 47, qsgmii)
|
|
SWITCH_PORT(47, 48, qsgmii)
|
|
|
|
port@52 {
|
|
ethernet = <ðernet0>;
|
|
reg = <52>;
|
|
phy-mode = "internal";
|
|
|
|
fixed-link {
|
|
speed = <1000>;
|
|
full-duplex;
|
|
};
|
|
};
|
|
};
|
|
};
|