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be0639063a
Merged upstream: bcm27xx/patches-5.4/950-1014-Revert-mailbox-avoid-timer-start-from-callback.patch generic/backport-5.4/080-wireguard-0021-crypto-blake2s-generic-C-library-implementation-and-.patch Manually adapted: layerscape/patches-5.4/801-audio-0005-Revert-ASoC-fsl_sai-Add-support-for-SAI-new-version.patch oxnas/patches-5.4/100-oxnas-clk-plla-pllb.patch Compile-tested: lantiq/xrx200 Run-tested: lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
46 lines
1.3 KiB
Diff
46 lines
1.3 KiB
Diff
From: MarkLee <Mark-MC.Lee@mediatek.com>
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Date: Wed, 13 Nov 2019 10:38:43 +0800
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Subject: [PATCH] net: ethernet: mediatek: Refine the timing of GDM/PSE setup
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Refine the timing of GDM/PSE setup, move it from mtk_hw_init
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to mtk_open. This is recommended by the mt762x HW design to
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do GDM/PSE setup only after PDMA has been started.
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We exclude mt7628 in mtk_gdm_config function since it is a old IP
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and there is no GDM/PSE block on it.
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Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -2256,6 +2256,9 @@ static void mtk_gdm_config(struct mtk_et
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{
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int i;
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+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
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+ return;
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+
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for (i = 0; i < MTK_MAC_COUNT; i++) {
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u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
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@@ -2294,6 +2297,8 @@ static int mtk_open(struct net_device *d
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if (err)
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return err;
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+ mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
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+
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napi_enable(ð->tx_napi);
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napi_enable(ð->rx_napi);
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mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
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@@ -2477,8 +2482,6 @@ static int mtk_hw_init(struct mtk_eth *e
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mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
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mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
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- mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
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-
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return 0;
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err_disable_pm:
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