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9dae0ac0bc
Continuation of commit 8b66f1a. Set the switch address on the MDIO bus to 31.
This is required for all boards currently working with the mt7530 DSA driver.
Fixes: #15419
Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
558 lines
8.8 KiB
Plaintext
558 lines
8.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/* Copyright (c) 2022, Marcel Ziswiler <marcel@ziswiler.com> */
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/dts-v1/;
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#include "mt7622.dtsi"
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#include "mt6380.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "Netgear WAX206";
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compatible = "netgear,wax206", "mediatek,mt7622";
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aliases {
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ethernet0 = &gmac0;
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led-boot = &led_power_r;
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led-failsafe = &led_power_r;
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led-running = &led_power_g;
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led-upgrade = &led_power_g;
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serial0 = &uart0;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n8 swiotlb=512";
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};
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cpus {
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cpu@0 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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cpu@1 {
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proc-supply = <&mt6380_vcpu_reg>;
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sram-supply = <&mt6380_vm_reg>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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reset {
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gpios = <&pio 0 GPIO_ACTIVE_LOW>;
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label = "reset";
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linux,code = <KEY_RESTART>;
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};
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wps {
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gpios = <&pio 102 GPIO_ACTIVE_LOW>;
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label = "wps";
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led_power_r: power_red {
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default-state = "on";
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gpios = <&pio 3 GPIO_ACTIVE_LOW>;
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label = "power:red";
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};
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led_power_g: power_green {
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default-state = "off";
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gpios = <&pio 4 GPIO_ACTIVE_LOW>;
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label = "power:green";
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};
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inet_green {
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default-state = "off";
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gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
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label = "inet:green";
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};
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inet_blue {
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default-state = "off";
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gpios = <&pio 17 GPIO_ACTIVE_LOW>;
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label = "inet:blue";
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};
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wifin_green {
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default-state = "off";
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gpios = <&pio 85 GPIO_ACTIVE_LOW>;
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label = "wifin:green";
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};
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wifin_blue {
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default-state = "off";
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gpios = <&pio 86 GPIO_ACTIVE_LOW>;
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label = "wifin:blue";
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};
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wifia_green {
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default-state = "off";
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gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
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label = "wifia:green";
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};
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wifia_blue {
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default-state = "off";
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gpios = <&pio 1 GPIO_ACTIVE_LOW>;
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label = "wifia:blue";
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};
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};
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memory {
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reg = <0 0x40000000 0 0x40000000>;
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};
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};
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&bch {
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status = "okay";
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};
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&cir {
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pinctrl-names = "default";
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pinctrl-0 = <&irrx_pins>;
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status = "okay";
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};
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ð {
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pinctrl-names = "default";
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pinctrl-0 = <ð_pins>;
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status = "okay";
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gmac0: mac@0 {
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compatible = "mediatek,eth-mac";
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nvmem-cells = <&macaddr_factory_7fff4>;
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nvmem-cell-names = "mac-address";
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phy-mode = "2500base-x";
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reg = <0>;
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fixed-link {
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full-duplex;
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pause;
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speed = <2500>;
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};
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};
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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switch@1f {
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compatible = "mediatek,mt7531";
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reg = <31>;
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#interrupt-cells = <1>;
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interrupt-controller;
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interrupt-parent = <&pio>;
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interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
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reset-gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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label = "lan1";
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reg = <1>;
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};
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port@2 {
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label = "lan2";
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reg = <2>;
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};
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port@3 {
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label = "lan3";
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reg = <3>;
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};
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port@4 {
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label = "lan4";
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reg = <4>;
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};
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wan: port@5 {
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label = "wan";
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nvmem-cells = <&macaddr_factory_7fffa>;
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nvmem-cell-names = "mac-address";
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phy-handle = <&rtl8221b_phy>;
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phy-mode = "2500base-x";
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reg = <5>;
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};
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port@6 {
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ethernet = <&gmac0>;
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phy-mode = "2500base-x";
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reg = <6>;
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fixed-link {
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full-duplex;
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pause;
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speed = <2500>;
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};
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};
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};
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};
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rtl8221b_phy: ethernet-phy@7 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <7>;
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reset-gpios = <&pio 101 GPIO_ACTIVE_LOW>;
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interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
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reset-assert-us = <100000>;
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reset-deassert-us = <100000>;
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};
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};
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};
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&pcie0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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};
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&pcie1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie1_pins>;
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status = "okay";
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};
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&pio {
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eth_pins: eth-pins {
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mux {
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function = "eth";
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groups = "mdc_mdio", "rgmii_via_gmac2";
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};
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};
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irrx_pins: irrx-pins {
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mux {
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function = "ir";
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groups = "ir_1_rx";
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};
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};
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irtx_pins: irtx-pins {
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mux {
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function = "ir";
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groups = "ir_1_tx";
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};
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};
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pcie0_pins: pcie0-pins {
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mux {
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function = "pcie";
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groups = "pcie0_pad_perst",
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"pcie0_1_waken",
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"pcie0_1_clkreq";
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};
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};
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pcie1_pins: pcie1-pins {
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mux {
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function = "pcie";
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groups = "pcie1_pad_perst",
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"pcie1_0_waken",
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"pcie1_0_clkreq";
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};
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};
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pmic_bus_pins: pmic-bus-pins {
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mux {
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function = "pmic";
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groups = "pmic_bus";
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};
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};
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pwm7_pins: pwm1-2-pins {
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mux {
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function = "pwm";
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groups = "pwm_ch7_2";
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};
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};
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wled_pins: wled-pins {
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mux {
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function = "led";
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groups = "wled";
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};
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};
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/* Serial NAND is shared pin with SPI-NOR */
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serial_nand_pins: serial-nand-pins {
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mux {
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function = "flash";
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groups = "snfi";
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};
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};
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spic0_pins: spic0-pins {
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mux {
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function = "spi";
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groups = "spic0_0";
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};
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};
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spic1_pins: spic1-pins {
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mux {
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function = "spi";
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groups = "spic1_0";
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};
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};
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uart0_pins: uart0-pins {
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mux {
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function = "uart";
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groups = "uart0_0_tx_rx";
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};
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};
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uart2_pins: uart2-pins {
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mux {
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function = "uart";
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groups = "uart2_1_tx_rx";
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};
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};
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watchdog_pins: watchdog-pins {
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mux {
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function = "watchdog";
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groups = "watchdog";
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};
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};
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};
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&pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pwm7_pins>;
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status = "okay";
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};
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&pwrap {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_bus_pins>;
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status = "okay";
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};
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&rtc {
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status = "disabled";
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};
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&sata {
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status = "disabled";
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};
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&sata_phy {
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status = "disabled";
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};
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&slot0 {
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wmac1: mt7915@0,0 {
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reg = <0x0000 0 0 0 0>;
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ieee80211-freq-limit = <5000000 6000000>;
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};
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};
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&snfi {
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pinctrl-names = "default";
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pinctrl-0 = <&serial_nand_pins>;
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status = "okay";
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snand: flash@0 {
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compatible = "spi-nand";
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mediatek,bmt-table-size = <0x1000>;
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mediatek,bmt-v2;
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nand-ecc-engine = <&snfi>;
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reg = <0>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Preloader";
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reg = <0x00000 0x0080000>;
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read-only;
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};
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partition@80000 {
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label = "ATF";
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reg = <0x80000 0x0040000>;
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read-only;
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};
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partition@c0000 {
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label = "Bootloader";
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reg = <0xc0000 0x0080000>;
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read-only;
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};
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partition@140000 {
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label = "Config";
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reg = <0x140000 0x0080000>;
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};
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factory: partition@1c0000 {
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label = "Factory";
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reg = <0x1c0000 0x0100000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_factory_7fff4: macaddr@7fff4 {
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reg = <0x7fff4 0x6>;
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};
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macaddr_factory_7fffa: macaddr@7fffa {
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reg = <0x7fffa 0x6>;
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};
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};
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};
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partition@2c0000 {
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label = "firmware";
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reg = <0x2c0000 0x2600000>;
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x0 0x600000>;
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};
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partition@600000 {
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label = "ubi";
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reg = <0x600000 0x2000000>;
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};
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};
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partition@28c0000 {
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label = "firmware_backup";
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reg = <0x28c0000 0x2600000>;
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read-only;
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};
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partition@4ec0000 {
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label = "CFG";
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reg = <0x4ec0000 0x800000>;
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read-only;
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};
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partition@56c0000 {
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label = "RAE";
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reg = <0x56c0000 0x400000>;
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read-only;
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};
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partition@5ac0000 {
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label = "POT";
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reg = <0x5ac0000 0x100000>;
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read-only;
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};
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partition@5bc0000 {
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label = "Language";
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reg = <0x5bc0000 0x400000>;
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read-only;
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};
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partition@5fc0000 {
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label = "Traffic";
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reg = <0x5fc0000 0x200000>;
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read-only;
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};
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partition@61c0000 {
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label = "Cert";
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reg = <0x61c0000 0x100000>;
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read-only;
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};
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partition@62c0000 {
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label = "NTGRcryptK";
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reg = <0x62c0000 0x100000>;
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read-only;
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};
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partition@63c0000 {
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label = "NTGRcryptD";
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reg = <0x63c0000 0x500000>;
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read-only;
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};
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partition@68c0000 {
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label = "LOG";
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reg = <0x68c0000 0x100000>;
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read-only;
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};
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partition@69c0000 {
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label = "User_data";
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reg = <0x69c0000 0x640000>;
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read-only;
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};
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};
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spic0_pins>;
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status = "okay";
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};
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&spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&spic1_pins>;
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status = "okay";
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};
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&ssusb {
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status = "disabled";
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};
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&u3phy {
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status = "disabled";
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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};
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&watchdog {
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pinctrl-names = "default";
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pinctrl-0 = <&watchdog_pins>;
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status = "okay";
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};
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&wmac {
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mediatek,mtd-eeprom = <&factory 0x0000>;
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status = "okay";
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};
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&wmac1 {
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mediatek,mtd-eeprom = <&factory 0x05000>;
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};
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