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3ecfc24c51
Sync patch with upstream version and tag them.
Minor changes done to Pinctrl patch to support older kernel.
Patch automatically refreshed with make target/linux/refresh.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
(cherry picked from commit a5d23e3aee)
63 lines
2.2 KiB
Diff
63 lines
2.2 KiB
Diff
From c31d1cdd7bff1d2c13d435bb9d0c76bfaa332097 Mon Sep 17 00:00:00 2001
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From: Lorenzo Bianconi <lorenzo@kernel.org>
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Date: Tue, 12 Nov 2024 01:08:49 +0100
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Subject: [PATCH 1/6] clk: en7523: remove REG_PCIE*_{MEM,MEM_MASK}
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configuration
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REG_PCIE*_MEM and REG_PCIE*_MEM_MASK regs (PBUS_CSR memory region) are not
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part of the scu block on the EN7581 SoC and they are used to select the
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PCIE ports on the PBUS, so remove this configuration from the clock driver
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and set these registers in the PCIE host driver instead.
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This patch does not introduce any backward incompatibility since the dts
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for EN7581 SoC is not upstream yet.
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Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
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Link: https://lore.kernel.org/r/20241112-clk-en7581-syscon-v2-2-8ada5e394ae4@kernel.org
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/clk-en7523.c | 18 ------------------
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1 file changed, 18 deletions(-)
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--- a/drivers/clk/clk-en7523.c
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+++ b/drivers/clk/clk-en7523.c
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@@ -31,12 +31,6 @@
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#define REG_RESET_CONTROL_PCIE1 BIT(27)
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#define REG_RESET_CONTROL_PCIE2 BIT(26)
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/* EN7581 */
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-#define REG_PCIE0_MEM 0x00
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-#define REG_PCIE0_MEM_MASK 0x04
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-#define REG_PCIE1_MEM 0x08
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-#define REG_PCIE1_MEM_MASK 0x0c
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-#define REG_PCIE2_MEM 0x10
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-#define REG_PCIE2_MEM_MASK 0x14
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#define REG_NP_SCU_PCIC 0x88
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#define REG_NP_SCU_SSTR 0x9c
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#define REG_PCIE_XSI0_SEL_MASK GENMASK(14, 13)
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@@ -415,26 +409,14 @@ static void en7581_pci_disable(struct cl
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static int en7581_clk_hw_init(struct platform_device *pdev,
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void __iomem *np_base)
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{
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- void __iomem *pb_base;
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u32 val;
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- pb_base = devm_platform_ioremap_resource(pdev, 3);
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- if (IS_ERR(pb_base))
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- return PTR_ERR(pb_base);
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-
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val = readl(np_base + REG_NP_SCU_SSTR);
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val &= ~(REG_PCIE_XSI0_SEL_MASK | REG_PCIE_XSI1_SEL_MASK);
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writel(val, np_base + REG_NP_SCU_SSTR);
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val = readl(np_base + REG_NP_SCU_PCIC);
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writel(val | 3, np_base + REG_NP_SCU_PCIC);
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- writel(0x20000000, pb_base + REG_PCIE0_MEM);
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- writel(0xfc000000, pb_base + REG_PCIE0_MEM_MASK);
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- writel(0x24000000, pb_base + REG_PCIE1_MEM);
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- writel(0xfc000000, pb_base + REG_PCIE1_MEM_MASK);
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- writel(0x28000000, pb_base + REG_PCIE2_MEM);
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- writel(0xfc000000, pb_base + REG_PCIE2_MEM_MASK);
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-
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return 0;
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}
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