mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-28 09:39:00 +00:00
9131cb44ff
Introduce EN7581 SoC support with currently rfb board supported. This is a new 64bit SoC from Airoha that is currently almost fully supported upstream with only the DTS missing. Setting source-only waiting for the full upstream support to be completed. Link: https://github.com/openwrt/openwrt/pull/16730 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
101 lines
3.2 KiB
Diff
101 lines
3.2 KiB
Diff
From dc869a40d73ee6e9f47d683690ae507e30e56044 Mon Sep 17 00:00:00 2001
|
|
From: Lorenzo Bianconi <lorenzo@kernel.org>
|
|
Date: Wed, 3 Jul 2024 18:12:42 +0200
|
|
Subject: [PATCH 1/3] PCI: mediatek-gen3: Add mtk_gen3_pcie_pdata data
|
|
structure
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Introduce mtk_gen3_pcie_pdata data structure in order to define
|
|
multiple callbacks for each supported SoC.
|
|
|
|
This is a preliminary patch to introduce EN7581 PCIe support.
|
|
|
|
Link: https://lore.kernel.org/linux-pci/c193d1a87505d045e2e0ef33317bce17012ee095.1720022580.git.lorenzo@kernel.org
|
|
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
|
|
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
|
|
Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
|
|
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
|
Acked-by: Jianjun Wang <jianjun.wang@mediatek.com>
|
|
---
|
|
drivers/pci/controller/pcie-mediatek-gen3.c | 24 ++++++++++++++++++---
|
|
1 file changed, 21 insertions(+), 3 deletions(-)
|
|
|
|
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
|
|
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
|
|
@@ -100,6 +100,16 @@
|
|
#define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0)
|
|
#define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2)
|
|
|
|
+struct mtk_gen3_pcie;
|
|
+
|
|
+/**
|
|
+ * struct mtk_gen3_pcie_pdata - differentiate between host generations
|
|
+ * @power_up: pcie power_up callback
|
|
+ */
|
|
+struct mtk_gen3_pcie_pdata {
|
|
+ int (*power_up)(struct mtk_gen3_pcie *pcie);
|
|
+};
|
|
+
|
|
/**
|
|
* struct mtk_msi_set - MSI information for each set
|
|
* @base: IO mapped register base
|
|
@@ -131,6 +141,7 @@ struct mtk_msi_set {
|
|
* @msi_sets: MSI sets information
|
|
* @lock: lock protecting IRQ bit map
|
|
* @msi_irq_in_use: bit map for assigned MSI IRQ
|
|
+ * @soc: pointer to SoC-dependent operations
|
|
*/
|
|
struct mtk_gen3_pcie {
|
|
struct device *dev;
|
|
@@ -151,6 +162,8 @@ struct mtk_gen3_pcie {
|
|
struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM];
|
|
struct mutex lock;
|
|
DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM);
|
|
+
|
|
+ const struct mtk_gen3_pcie_pdata *soc;
|
|
};
|
|
|
|
/* LTSSM state in PCIE_LTSSM_STATUS_REG bit[28:24] */
|
|
@@ -904,7 +917,7 @@ static int mtk_pcie_setup(struct mtk_gen
|
|
usleep_range(10, 20);
|
|
|
|
/* Don't touch the hardware registers before power up */
|
|
- err = mtk_pcie_power_up(pcie);
|
|
+ err = pcie->soc->power_up(pcie);
|
|
if (err)
|
|
return err;
|
|
|
|
@@ -939,6 +952,7 @@ static int mtk_pcie_probe(struct platfor
|
|
pcie = pci_host_bridge_priv(host);
|
|
|
|
pcie->dev = dev;
|
|
+ pcie->soc = device_get_match_data(dev);
|
|
platform_set_drvdata(pdev, pcie);
|
|
|
|
err = mtk_pcie_setup(pcie);
|
|
@@ -1054,7 +1068,7 @@ static int mtk_pcie_resume_noirq(struct
|
|
struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);
|
|
int err;
|
|
|
|
- err = mtk_pcie_power_up(pcie);
|
|
+ err = pcie->soc->power_up(pcie);
|
|
if (err)
|
|
return err;
|
|
|
|
@@ -1074,8 +1088,12 @@ static const struct dev_pm_ops mtk_pcie_
|
|
mtk_pcie_resume_noirq)
|
|
};
|
|
|
|
+static const struct mtk_gen3_pcie_pdata mtk_pcie_soc_mt8192 = {
|
|
+ .power_up = mtk_pcie_power_up,
|
|
+};
|
|
+
|
|
static const struct of_device_id mtk_pcie_of_match[] = {
|
|
- { .compatible = "mediatek,mt8192-pcie" },
|
|
+ { .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mtk_pcie_of_match);
|