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793f8ab62c
Add kernel patches for version 6.1. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
59 lines
1.7 KiB
Diff
59 lines
1.7 KiB
Diff
From e73d889889d4795cc1640ec0a6f813bfe585b838 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Thu, 4 May 2023 16:09:49 +0100
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Subject: [PATCH] bcm2711-rpi-ds: Switch to dma40 channel for hdmi
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audio
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Also tweak the flags:
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Remove NO_WAIT_RESP (27)
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Add BURST_LENGTH (30)
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The AXI path from DMA controller to HDMI audio fifo
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is long, and may have considerable delay.
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When using DMA without waiting for responses it is
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very easy to overfill the fifo as when the fifo
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removes DREQ there may be large numbers of writes
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in flight.
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This means the DREQ fifo threshold must be set low
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enough to accommodate the maximum number of in flight
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writes (unknown by something like 24),
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which means the 32 element fifo only requests data
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when it contains fewer than 8 entries, making it
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susceptable to underflow.
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If we wait for write responses we can set the DREQ
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fifo threshold much higher as there are a controlled
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number of writes in flight.
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However the overall bandwidth is reduced by setting
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this, so also enable a burstsize of 4 to improve
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bandwidth.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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arch/arm/boot/dts/bcm2711-rpi-ds.dtsi | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/arch/arm/boot/dts/bcm2711-rpi-ds.dtsi
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+++ b/arch/arm/boot/dts/bcm2711-rpi-ds.dtsi
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@@ -364,7 +364,7 @@
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<&firmware_clocks 14>,
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<&dvp 0>,
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<&clk_27MHz>;
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- dmas = <&dma (10|(1<<27)|(1<<24)|(10<<16)|(15<<20))>;
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+ dmas = <&dma40 (10|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
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status = "disabled";
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};
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@@ -397,7 +397,7 @@
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<&firmware_clocks 14>,
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<&dvp 1>,
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<&clk_27MHz>;
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- dmas = <&dma (17|(1<<27)|(1<<24)|(10<<16)|(15<<20))>;
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+ dmas = <&dma40 (17|(1<<30)|(1<<24)|(10<<16)|(15<<20))>;
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status = "disabled";
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};
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