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d374e0346e
0001-MIPS-lantiq-add-pcie-driver.patch needs to drop
MODULE_SUPPORTED_DEVICE because that macro is gone on newer kernels.
Add checks for copy_{to,from}_user in
0008-MIPS-lantiq-backport-old-timer-code.patch which is now mandatory.
0705-v5.13-net-dsa-lantiq-allow-to-use-all-GPHYs-on-xRX300-and-.patch
get dropped because it's a backport from Linux 5.13.
All other patches are refreshed.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
483 lines
14 KiB
Diff
483 lines
14 KiB
Diff
From 9afadf01b1be371ee88491819aa67364684461f9 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Fri, 3 Aug 2012 10:27:25 +0200
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Subject: [PATCH 04/36] MIPS: lantiq: add atm hack
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/include/asm/mach-lantiq/lantiq_atm.h | 196 +++++++++++++++++++++++
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arch/mips/include/asm/mach-lantiq/lantiq_ptm.h | 203 ++++++++++++++++++++++++
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arch/mips/lantiq/irq.c | 2 +
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arch/mips/mm/cache.c | 4 +
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include/uapi/linux/atm.h | 6 +
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net/atm/common.c | 6 +
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net/atm/proc.c | 2 +-
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7 files changed, 416 insertions(+), 1 deletion(-)
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create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_atm.h
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create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq_atm.h
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@@ -0,0 +1,196 @@
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+/******************************************************************************
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+**
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+** FILE NAME : ifx_atm.h
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+** PROJECT : UEIP
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+** MODULES : ATM
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+**
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+** DATE : 17 Jun 2009
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+** AUTHOR : Xu Liang
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+** DESCRIPTION : Global ATM driver header file
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+** COPYRIGHT : Copyright (c) 2006
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+** Infineon Technologies AG
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+** Am Campeon 1-12, 85579 Neubiberg, Germany
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+**
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+** This program is free software; you can redistribute it and/or modify
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+** it under the terms of the GNU General Public License as published by
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+** the Free Software Foundation; either version 2 of the License, or
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+** (at your option) any later version.
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+**
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+** HISTORY
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+** $Date $Author $Comment
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+** 07 JUL 2009 Xu Liang Init Version
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+*******************************************************************************/
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+
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+#ifndef IFX_ATM_H
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+#define IFX_ATM_H
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+
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+
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+
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+/*!
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+ \defgroup IFX_ATM UEIP Project - ATM driver module
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+ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9.
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+ */
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+
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+/*!
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+ \defgroup IFX_ATM_IOCTL IOCTL Commands
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+ \ingroup IFX_ATM
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+ \brief IOCTL Commands used by user application.
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+ */
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+
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+/*!
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+ \defgroup IFX_ATM_STRUCT Structures
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+ \ingroup IFX_ATM
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+ \brief Structures used by user application.
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+ */
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+
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+/*!
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+ \file ifx_atm.h
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+ \ingroup IFX_ATM
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+ \brief ATM driver header file
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+ */
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+
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+
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+
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+/*
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+ * ####################################
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+ * Definition
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+ * ####################################
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+ */
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+
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+/*!
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+ \addtogroup IFX_ATM_STRUCT
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+ */
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+/*@{*/
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+
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+/*
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+ * ATM MIB
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+ */
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+
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+/*!
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+ \struct atm_cell_ifEntry_t
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+ \brief Structure used for Cell Level MIB Counters.
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+
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+ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL".
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+ */
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+typedef struct {
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+ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */
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+ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */
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+ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */
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+ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */
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+ __u32 ifInErrors; /*!< counter of error ingress cells */
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+ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */
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+ __u32 ifOutErrors; /*!< counter of error egress cells */
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+} atm_cell_ifEntry_t;
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+
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+/*!
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+ \struct atm_aal5_ifEntry_t
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+ \brief Structure used for AAL5 Frame Level MIB Counters.
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+
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+ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5".
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+ */
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+typedef struct {
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+ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */
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+ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */
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+ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */
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+ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */
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+ __u32 ifInUcastPkts; /*!< counter of ingress packets */
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+ __u32 ifOutUcastPkts; /*!< counter of egress packets */
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+ __u32 ifInErrors; /*!< counter of error ingress packets */
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+ __u32 ifInDiscards; /*!< counter of dropped ingress packets */
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+ __u32 ifOutErros; /*!< counter of error egress packets */
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+ __u32 ifOutDiscards; /*!< counter of dropped egress packets */
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+} atm_aal5_ifEntry_t;
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+
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+/*!
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+ \struct atm_aal5_vcc_t
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+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
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+
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+ This structure is a part of structure "atm_aal5_vcc_x_t".
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+ */
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+typedef struct {
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+ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */
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+ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet
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+ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */
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+} atm_aal5_vcc_t;
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+
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+/*!
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+ \struct atm_aal5_vcc_x_t
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+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters.
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+
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+ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC".
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+ */
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+typedef struct {
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+ int vpi; /*!< VPI of the VCC to get MIB counters */
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+ int vci; /*!< VCI of the VCC to get MIB counters */
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+ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */
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+} atm_aal5_vcc_x_t;
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+
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+/*@}*/
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+
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+
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+
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+/*
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+ * ####################################
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+ * IOCTL
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+ * ####################################
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+ */
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+
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+/*!
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+ \addtogroup IFX_ATM_IOCTL
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+ */
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+/*@{*/
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+
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+/*
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+ * ioctl Command
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+ */
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+/*!
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+ \brief ATM IOCTL Magic Number
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+ */
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+#define PPE_ATM_IOC_MAGIC 'o'
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+/*!
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+ \brief ATM IOCTL Command - Get Cell Level MIB Counters
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+
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+ This command is obsolete. User can get cell level MIB from DSL API.
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+ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters.
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+ */
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+#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t)
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+/*!
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+ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters
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+
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+ Get AAL5 packet counters.
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+ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters.
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+ */
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+#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t)
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+/*!
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+ \brief ATM IOCTL Command - Get Per PVC MIB Counters
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+
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+ Get AAL5 packet counters for each PVC.
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+ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters.
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+ */
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+#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t)
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+/*!
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+ \brief Total Number of ATM IOCTL Commands
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+ */
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+#define PPE_ATM_IOC_MAXNR 3
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+
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+/*@}*/
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+
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+
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+
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+/*
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+ * ####################################
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+ * API
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+ * ####################################
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+ */
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+
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+#ifdef __KERNEL__
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+struct port_cell_info {
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+ unsigned int port_num;
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+ unsigned int tx_link_rate[2];
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+};
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+#endif
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+
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+
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+
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+#endif // IFX_ATM_H
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+
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--- /dev/null
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+++ b/arch/mips/include/asm/mach-lantiq/lantiq_ptm.h
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@@ -0,0 +1,203 @@
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+/******************************************************************************
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+**
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+** FILE NAME : ifx_ptm.h
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+** PROJECT : UEIP
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+** MODULES : PTM
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+**
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+** DATE : 17 Jun 2009
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+** AUTHOR : Xu Liang
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+** DESCRIPTION : Global PTM driver header file
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+** COPYRIGHT : Copyright (c) 2006
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+** Infineon Technologies AG
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+** Am Campeon 1-12, 85579 Neubiberg, Germany
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+**
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+** This program is free software; you can redistribute it and/or modify
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+** it under the terms of the GNU General Public License as published by
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+** the Free Software Foundation; either version 2 of the License, or
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+** (at your option) any later version.
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+**
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+** HISTORY
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+** $Date $Author $Comment
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+** 07 JUL 2009 Xu Liang Init Version
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+*******************************************************************************/
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+
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+#ifndef IFX_PTM_H
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+#define IFX_PTM_H
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+
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+
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+
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+/*!
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+ \defgroup IFX_PTM UEIP Project - PTM driver module
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+ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9.
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+ */
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+
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+/*!
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+ \defgroup IFX_PTM_IOCTL IOCTL Commands
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+ \ingroup IFX_PTM
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+ \brief IOCTL Commands used by user application.
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+ */
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+
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+/*!
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+ \defgroup IFX_PTM_STRUCT Structures
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+ \ingroup IFX_PTM
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+ \brief Structures used by user application.
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+ */
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+
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+/*!
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+ \file ifx_ptm.h
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+ \ingroup IFX_PTM
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+ \brief PTM driver header file
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+ */
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+
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+
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+
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+/*
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+ * ####################################
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+ * Definition
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+ * ####################################
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+ */
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+
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+
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+
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+/*
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+ * ####################################
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+ * IOCTL
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+ * ####################################
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+ */
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+
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+/*!
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+ \addtogroup IFX_PTM_IOCTL
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+ */
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+/*@{*/
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+
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+/*
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+ * ioctl Command
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+ */
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+/*!
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+ \brief PTM IOCTL Command - Get codeword MIB counters.
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+
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+ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters.
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+ */
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+#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1
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+/*!
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+ \brief PTM IOCTL Command - Get packet MIB counters.
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+
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+ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters.
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+ */
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+#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2
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+/*!
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+ \brief PTM IOCTL Command - Get firmware configuration (CRC).
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+
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+ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC).
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+ */
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+#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3
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+/*!
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+ \brief PTM IOCTL Command - Set firmware configuration (CRC).
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+
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+ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC).
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+ */
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+#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4
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+/*!
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+ \brief PTM IOCTL Command - Program priority value to TX queue mapping.
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+
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+ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping.
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+ */
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+#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14
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+
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+/*@}*/
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+
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+
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+/*!
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+ \addtogroup IFX_PTM_STRUCT
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+ */
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+/*@{*/
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+
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+/*
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+ * ioctl Data Type
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+ */
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+
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+/*!
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+ \typedef PTM_CW_IF_ENTRY_T
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+ \brief Wrapping of structure "ptm_cw_ifEntry_t".
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+ */
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+/*!
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+ \struct ptm_cw_ifEntry_t
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+ \brief Structure used for CodeWord level MIB counters.
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+ */
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+typedef struct ptm_cw_ifEntry_t {
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+ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */
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+ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */
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+ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */
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+ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */
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+ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */
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+} PTM_CW_IF_ENTRY_T;
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+
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+/*!
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+ \typedef PTM_FRAME_MIB_T
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+ \brief Wrapping of structure "ptm_frame_mib_t".
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+ */
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+/*!
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+ \struct ptm_frame_mib_t
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+ \brief Structure used for packet level MIB counters.
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+ */
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+typedef struct ptm_frame_mib_t {
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+ uint32_t RxCorrect; /*!< output, number of ingress packet */
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+ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */
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+ uint32_t RxDropped; /*!< output, number of dropped ingress packet */
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+ uint32_t TxSend; /*!< output, number of egress packet */
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+} PTM_FRAME_MIB_T;
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+
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+/*!
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+ \typedef IFX_PTM_CFG_T
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+ \brief Wrapping of structure "ptm_cfg_t".
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+ */
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+/*!
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+ \struct ptm_cfg_t
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+ \brief Structure used for ETH/TC CRC configuration.
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+ */
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+typedef struct ptm_cfg_t {
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+ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */
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+ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */
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+ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */
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+ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */
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+ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */
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+ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */
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+ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */
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+} IFX_PTM_CFG_T;
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+
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+/*!
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+ \typedef IFX_PTM_PRIO_Q_MAP_T
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+ \brief Wrapping of structure "ppe_prio_q_map".
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+ */
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+/*!
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+ \struct ppe_prio_q_map
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+ \brief Structure used for Priority Value to TX Queue mapping.
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+ */
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+typedef struct ppe_prio_q_map {
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+ int pkt_prio;
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+ int qid;
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+ int vpi; // ignored in eth interface
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+ int vci; // ignored in eth interface
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+} IFX_PTM_PRIO_Q_MAP_T;
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+
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+/*@}*/
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+
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+
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+
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+/*
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+ * ####################################
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+ * API
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+ * ####################################
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+ */
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+
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+#ifdef __KERNEL__
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+struct port_cell_info {
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+ unsigned int port_num;
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+ unsigned int tx_link_rate[2];
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+};
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+#endif
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+
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+
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+
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+#endif // IFX_PTM_H
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+
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--- a/arch/mips/lantiq/irq.c
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+++ b/arch/mips/lantiq/irq.c
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@@ -13,6 +13,7 @@
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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+#include <linux/module.h>
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#include <asm/bootinfo.h>
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#include <asm/irq_cpu.h>
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@@ -92,6 +93,7 @@ void ltq_disable_irq(struct irq_data *d)
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}
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raw_spin_unlock_irqrestore(<q_icu_lock, flags);
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}
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+EXPORT_SYMBOL(ltq_mask_and_ack_irq);
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void ltq_mask_and_ack_irq(struct irq_data *d)
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{
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--- a/arch/mips/mm/cache.c
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+++ b/arch/mips/mm/cache.c
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@@ -63,6 +63,10 @@ void (*_dma_cache_wback_inv)(unsigned lo
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void (*_dma_cache_wback)(unsigned long start, unsigned long size);
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void (*_dma_cache_inv)(unsigned long start, unsigned long size);
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+EXPORT_SYMBOL(_dma_cache_wback_inv);
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+EXPORT_SYMBOL(_dma_cache_wback);
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+EXPORT_SYMBOL(_dma_cache_inv);
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+
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#endif /* CONFIG_DMA_NONCOHERENT */
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/*
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--- a/include/uapi/linux/atm.h
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+++ b/include/uapi/linux/atm.h
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@@ -131,8 +131,14 @@
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#define ATM_ABR 4
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#define ATM_ANYCLASS 5 /* compatible with everything */
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+#define ATM_VBR_NRT ATM_VBR
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+#define ATM_VBR_RT 6
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+#define ATM_UBR_PLUS 7
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+#define ATM_GFR 8
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+
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#define ATM_MAX_PCR -1 /* maximum available PCR */
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+
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struct atm_trafprm {
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unsigned char traffic_class; /* traffic class (ATM_UBR, ...) */
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int max_pcr; /* maximum PCR in cells per second */
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--- a/net/atm/proc.c
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+++ b/net/atm/proc.c
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@@ -141,7 +141,7 @@ static void *vcc_seq_next(struct seq_fil
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static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
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{
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static const char *const class_name[] = {
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- "off", "UBR", "CBR", "VBR", "ABR"};
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+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
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static const char *const aal_name[] = {
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"---", "1", "2", "3/4", /* 0- 3 */
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"???", "5", "???", "???", /* 4- 7 */
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