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662d1f9f8d
Removed upstreamed:
generic/backport-5.10/350-v5.18-MIPS-pgalloc-fix-memory-leak-caused-by-pgd_free.patch
generic/pending-5.10/850-0014-PCI-aardvark-Fix-reading-PCI_EXP_RTSTA_PME-bit-on-em.patch
ipq40xx/patches-5.10/105-ipq40xx-fix-sleep-clock.patch
All patches automatically rebased.
Build system: x86_64
Build-tested: bcm2711/RPi4B, mt7622/RT3200
Run-tested: bcm2711/RPi4B, mt7622/RT3200
Compile-/run-tested: ath79/generic (Archer C7 v2).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
[rebased in 22.03 tree]
Signed-off-by: John Audia <graysky@archlinux.us>
(cherry picked from commit b92ec82235)
92 lines
3.2 KiB
Diff
92 lines
3.2 KiB
Diff
From fa73c200f181436eab859374657c53a73778d8ad Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
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Date: Fri, 26 Mar 2021 17:35:44 +0100
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Subject: [PATCH] PCI: aardvark: Fix setting MSI address
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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MSI address for receiving MSI interrupts needs to be correctly set before
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enabling processing of MSI interrupts.
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Move code for setting PCIE_MSI_ADDR_LOW_REG and PCIE_MSI_ADDR_HIGH_REG
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from advk_pcie_init_msi_irq_domain() to advk_pcie_setup_hw(), before
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enabling PCIE_CORE_CTRL2_MSI_ENABLE.
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After this we can remove the now unused member msi_msg, which was used
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only for MSI doorbell address. MSI address can be any address which cannot
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be used to DMA to. So change it to the address of the main struct advk_pcie.
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Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver")
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Signed-off-by: Pali Rohár <pali@kernel.org>
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Acked-by: Marc Zyngier <maz@kernel.org>
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Signed-off-by: Marek Behún <kabel@kernel.org>
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Cc: stable@vger.kernel.org # f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support")
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---
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drivers/pci/controller/pci-aardvark.c | 21 +++++++++------------
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1 file changed, 9 insertions(+), 12 deletions(-)
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--- a/drivers/pci/controller/pci-aardvark.c
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+++ b/drivers/pci/controller/pci-aardvark.c
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@@ -284,7 +284,6 @@ struct advk_pcie {
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raw_spinlock_t msi_irq_lock;
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DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
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struct mutex msi_used_lock;
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- u16 msi_msg;
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int link_gen;
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struct pci_bridge_emul bridge;
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struct gpio_desc *reset_gpio;
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@@ -479,6 +478,7 @@ static void advk_pcie_disable_ob_win(str
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static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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{
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+ phys_addr_t msi_addr;
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u32 reg;
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int i;
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@@ -567,6 +567,11 @@ static void advk_pcie_setup_hw(struct ad
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reg |= LANE_COUNT_1;
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advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
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+ /* Set MSI address */
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+ msi_addr = virt_to_phys(pcie);
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+ advk_writel(pcie, lower_32_bits(msi_addr), PCIE_MSI_ADDR_LOW_REG);
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+ advk_writel(pcie, upper_32_bits(msi_addr), PCIE_MSI_ADDR_HIGH_REG);
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+
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/* Enable MSI */
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reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
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reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
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@@ -1186,10 +1191,10 @@ static void advk_msi_irq_compose_msi_msg
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struct msi_msg *msg)
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{
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struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
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- phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
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+ phys_addr_t msi_addr = virt_to_phys(pcie);
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- msg->address_lo = lower_32_bits(msi_msg);
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- msg->address_hi = upper_32_bits(msi_msg);
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+ msg->address_lo = lower_32_bits(msi_addr);
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+ msg->address_hi = upper_32_bits(msi_addr);
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msg->data = data->hwirq;
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}
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@@ -1348,18 +1353,10 @@ static struct msi_domain_info advk_msi_d
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static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
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{
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struct device *dev = &pcie->pdev->dev;
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- phys_addr_t msi_msg_phys;
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raw_spin_lock_init(&pcie->msi_irq_lock);
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mutex_init(&pcie->msi_used_lock);
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- msi_msg_phys = virt_to_phys(&pcie->msi_msg);
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-
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- advk_writel(pcie, lower_32_bits(msi_msg_phys),
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- PCIE_MSI_ADDR_LOW_REG);
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- advk_writel(pcie, upper_32_bits(msi_msg_phys),
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- PCIE_MSI_ADDR_HIGH_REG);
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-
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pcie->msi_inner_domain =
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irq_domain_add_linear(NULL, MSI_IRQ_NUM,
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&advk_msi_domain_ops, pcie);
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