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https://github.com/openwrt/openwrt.git
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7b0e1d28e8
Refreshed all patches. Compile-tested on: cns3xxx, imx6 Runtime-tested on: cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
74 lines
2.3 KiB
Diff
74 lines
2.3 KiB
Diff
--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -142,20 +142,29 @@ static int read_fsr(struct spi_nor *nor)
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* location. Return the configuration register value.
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* Returns negative if error occurred.
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*/
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-static int read_cr(struct spi_nor *nor)
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+static int _read_cr(struct spi_nor *nor, u8 reg)
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{
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int ret;
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u8 val;
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- ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
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+ ret = nor->read_reg(nor, reg, &val, 1);
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if (ret < 0) {
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- dev_err(nor->dev, "error %d reading CR\n", ret);
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+ dev_err(nor->dev, "error %d reading %s\n", ret,
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+ (reg==SPINOR_OP_RDCR)?"CR":"XCR");
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return ret;
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}
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return val;
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}
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+static inline int read_cr(struct spi_nor *nor) {
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+ return _read_cr(nor, SPINOR_OP_RDCR);
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+}
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+
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+static inline int read_xcr(struct spi_nor *nor) {
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+ return _read_cr(nor, SPINOR_OP_RDXCR);
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+}
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+
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/*
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* Write status register 1 byte
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* Returns negative if error occurred.
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@@ -2888,9 +2897,16 @@ int spi_nor_scan(struct spi_nor *nor, co
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} else if (mtd->size > 0x1000000) {
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/* enable 4-byte addressing if the device exceeds 16MiB */
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nor->addr_width = 4;
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- if (info->flags & SPI_NOR_4B_READ_OP)
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- spi_nor_set_4byte_read(nor, info);
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- else if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
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+ if (info->flags & SPI_NOR_4B_READ_OP) {
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+ if (JEDEC_MFR(info) == SNOR_MFR_WINBOND) {
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+ ret = read_xcr(nor);
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+ if (!(ret > 0 && (ret & XCR_DEF_4B_ADDR_MODE)))
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+ spi_nor_set_4byte_read(nor, info);
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+ else
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+ set_4byte(nor, info, 1);
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+ } else
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+ spi_nor_set_4byte_read(nor, info);
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+ } else if (JEDEC_MFR(info) == SNOR_MFR_SPANSION ||
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info->flags & SPI_NOR_4B_OPCODES)
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spi_nor_set_4byte_opcodes(nor, info);
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else
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--- a/include/linux/mtd/spi-nor.h
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+++ b/include/linux/mtd/spi-nor.h
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@@ -103,6 +103,7 @@
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#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
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#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
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#define SPINOR_OP_WREAR 0xc5 /* Write extended address register */
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+#define SPINOR_OP_RDXCR 0x15 /* Read extended configuration register */
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/* Used for Spansion flashes only. */
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#define SPINOR_OP_BRWR 0x17 /* Bank register write */
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@@ -135,6 +136,7 @@
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/* Configuration Register bits. */
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#define CR_QUAD_EN_SPAN BIT(1) /* Spansion Quad I/O */
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+#define XCR_DEF_4B_ADDR_MODE BIT(1) /* Winbond 4B mode default */
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/* Status Register 2 bits. */
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#define SR2_QUAD_EN_BIT7 BIT(7)
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