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https://github.com/openwrt/openwrt.git
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293caa16a0
Refresh pending patches with make target/linux/refresh. Signed-off-by: Weijie Gao <hackpascal@gmail.com>
372 lines
10 KiB
Diff
372 lines
10 KiB
Diff
From 4b1a2716299c0e96a698044aebf3f80513509ae7 Mon Sep 17 00:00:00 2001
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From: Daniel Golle <daniel@makrotopia.org>
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Date: Tue, 12 Dec 2023 03:47:18 +0000
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Subject: [PATCH 3/5] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988
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Introduce a proper platform MFD driver for the LynxI (H)SGMII PCS which
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is going to initially be used for the MT7988 SoC.
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Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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---
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drivers/net/pcs/pcs-mtk-lynxi.c | 227 ++++++++++++++++++++++++++++--
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include/linux/pcs/pcs-mtk-lynxi.h | 11 ++
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2 files changed, 227 insertions(+), 11 deletions(-)
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--- a/drivers/net/pcs/pcs-mtk-lynxi.c
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+++ b/drivers/net/pcs/pcs-mtk-lynxi.c
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018-2019 MediaTek Inc.
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-/* A library for MediaTek SGMII circuit
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+/* A library and platform driver for the MediaTek LynxI SGMII circuit
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*
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* Author: Sean Wang <sean.wang@mediatek.com>
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* Author: Alexander Couzens <lynxis@fe80.eu>
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@@ -8,11 +8,17 @@
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*
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*/
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+#include <linux/clk.h>
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#include <linux/mdio.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/mutex.h>
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#include <linux/of.h>
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+#include <linux/of_platform.h>
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#include <linux/pcs/pcs-mtk-lynxi.h>
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#include <linux/phylink.h>
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+#include <linux/platform_device.h>
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#include <linux/regmap.h>
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+#include <linux/reset.h>
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/* SGMII subsystem config registers */
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/* BMCR (low 16) BMSR (high 16) */
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@@ -65,6 +71,8 @@
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#define SGMII_PN_SWAP_MASK GENMASK(1, 0)
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#define SGMII_PN_SWAP_TX_RX (BIT(0) | BIT(1))
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+#define MTK_NETSYS_V3_AMA_RGC3 0x128
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+
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/* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
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* data
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* @regmap: The register map pointing at the range used to setup
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@@ -74,15 +82,29 @@
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* @interface: Currently configured interface mode
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* @pcs: Phylink PCS structure
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* @flags: Flags indicating hardware properties
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+ * @rstc: Reset controller
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+ * @sgmii_sel: SGMII Register Clock
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+ * @sgmii_rx: SGMII RX Clock
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+ * @sgmii_tx: SGMII TX Clock
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+ * @node: List node
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*/
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struct mtk_pcs_lynxi {
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struct regmap *regmap;
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+ struct device *dev;
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u32 ana_rgc3;
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phy_interface_t interface;
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struct phylink_pcs pcs;
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u32 flags;
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+ struct reset_control *rstc;
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+ struct clk *sgmii_sel;
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+ struct clk *sgmii_rx;
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+ struct clk *sgmii_tx;
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+ struct list_head node;
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};
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+static LIST_HEAD(mtk_pcs_lynxi_instances);
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+static DEFINE_MUTEX(instance_mutex);
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+
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static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs)
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{
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return container_of(pcs, struct mtk_pcs_lynxi, pcs);
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@@ -102,6 +124,17 @@ static void mtk_pcs_lynxi_get_state(stru
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FIELD_GET(SGMII_LPA, adv));
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}
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+static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
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+{
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+ if (!mpcs->rstc)
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+ return;
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+
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+ reset_control_assert(mpcs->rstc);
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+ udelay(100);
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+ reset_control_deassert(mpcs->rstc);
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+ mdelay(1);
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+}
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+
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static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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@@ -147,6 +180,7 @@ static int mtk_pcs_lynxi_config(struct p
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SGMII_PHYA_PWD);
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/* Reset SGMII PCS state */
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+ mtk_sgmii_reset(mpcs);
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regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
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SGMII_SW_RESET);
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@@ -233,10 +267,29 @@ static void mtk_pcs_lynxi_link_up(struct
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}
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}
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+static int mtk_pcs_lynxi_enable(struct phylink_pcs *pcs)
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+{
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+ struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
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+
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+ if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
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+ clk_prepare_enable(mpcs->sgmii_rx);
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+ clk_prepare_enable(mpcs->sgmii_tx);
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+ }
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+
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+ return 0;
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+}
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+
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static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
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{
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struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
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+ regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
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+
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+ if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
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+ clk_disable_unprepare(mpcs->sgmii_tx);
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+ clk_disable_unprepare(mpcs->sgmii_rx);
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+ }
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+
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mpcs->interface = PHY_INTERFACE_MODE_NA;
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}
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@@ -246,11 +299,12 @@ static const struct phylink_pcs_ops mtk_
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.pcs_an_restart = mtk_pcs_lynxi_restart_an,
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.pcs_link_up = mtk_pcs_lynxi_link_up,
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.pcs_disable = mtk_pcs_lynxi_disable,
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+ .pcs_enable = mtk_pcs_lynxi_enable,
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};
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-struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
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- struct regmap *regmap, u32 ana_rgc3,
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- u32 flags)
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+static struct phylink_pcs *mtk_pcs_lynxi_init(struct device *dev, struct regmap *regmap,
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+ u32 ana_rgc3, u32 flags,
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+ struct mtk_pcs_lynxi *prealloc)
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{
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struct mtk_pcs_lynxi *mpcs;
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u32 id, ver;
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@@ -258,29 +312,33 @@ struct phylink_pcs *mtk_pcs_lynxi_create
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ret = regmap_read(regmap, SGMSYS_PCS_DEVICE_ID, &id);
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if (ret < 0)
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- return NULL;
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+ return ERR_PTR(ret);
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if (id != SGMII_LYNXI_DEV_ID) {
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dev_err(dev, "unknown PCS device id %08x\n", id);
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- return NULL;
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+ return ERR_PTR(-ENODEV);
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}
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ret = regmap_read(regmap, SGMSYS_PCS_SCRATCH, &ver);
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if (ret < 0)
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- return NULL;
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+ return ERR_PTR(ret);
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ver = FIELD_GET(SGMII_DEV_VERSION, ver);
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if (ver != 0x1) {
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dev_err(dev, "unknown PCS device version %04x\n", ver);
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- return NULL;
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+ return ERR_PTR(-ENODEV);
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}
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dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id,
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ver);
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- mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
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- if (!mpcs)
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- return NULL;
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+ if (prealloc) {
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+ mpcs = prealloc;
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+ } else {
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+ mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
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+ if (!mpcs)
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+ return ERR_PTR(-ENOMEM);
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+ };
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mpcs->ana_rgc3 = ana_rgc3;
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mpcs->regmap = regmap;
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@@ -291,6 +349,13 @@ struct phylink_pcs *mtk_pcs_lynxi_create
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mpcs->interface = PHY_INTERFACE_MODE_NA;
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return &mpcs->pcs;
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+};
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+
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+struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
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+ struct regmap *regmap, u32 ana_rgc3,
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+ u32 flags)
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+{
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+ return mtk_pcs_lynxi_init(dev, regmap, ana_rgc3, flags, NULL);
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}
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EXPORT_SYMBOL(mtk_pcs_lynxi_create);
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@@ -303,4 +368,144 @@ void mtk_pcs_lynxi_destroy(struct phylin
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}
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EXPORT_SYMBOL(mtk_pcs_lynxi_destroy);
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+static int mtk_pcs_lynxi_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct device_node *np = dev->of_node;
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+ struct mtk_pcs_lynxi *mpcs;
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+ struct phylink_pcs *pcs;
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+ struct regmap *regmap;
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+ u32 flags = 0;
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+
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+ mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
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+ if (!mpcs)
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+ return -ENOMEM;
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+
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+ mpcs->dev = dev;
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+ regmap = syscon_node_to_regmap(np->parent);
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+ if (IS_ERR(regmap))
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+ return PTR_ERR(regmap);
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+
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+ if (of_property_read_bool(np->parent, "mediatek,pnswap"))
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+ flags |= MTK_SGMII_FLAG_PN_SWAP;
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+
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+ mpcs->rstc = of_reset_control_get_shared(np->parent, NULL);
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+ if (IS_ERR(mpcs->rstc))
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+ return PTR_ERR(mpcs->rstc);
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+
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+ reset_control_deassert(mpcs->rstc);
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+ mpcs->sgmii_sel = devm_clk_get_enabled(dev, "sgmii_sel");
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+ if (IS_ERR(mpcs->sgmii_sel))
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+ return PTR_ERR(mpcs->sgmii_sel);
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+
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+ mpcs->sgmii_rx = devm_clk_get(dev, "sgmii_rx");
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+ if (IS_ERR(mpcs->sgmii_rx))
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+ return PTR_ERR(mpcs->sgmii_rx);
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+
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+ mpcs->sgmii_tx = devm_clk_get(dev, "sgmii_tx");
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+ if (IS_ERR(mpcs->sgmii_tx))
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+ return PTR_ERR(mpcs->sgmii_tx);
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+
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+ pcs = mtk_pcs_lynxi_init(dev, regmap, (uintptr_t)of_device_get_match_data(dev),
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+ flags, mpcs);
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+ if (IS_ERR(pcs))
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+ return PTR_ERR(pcs);
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+
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+ regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
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+
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+ platform_set_drvdata(pdev, mpcs);
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+
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+ mutex_lock(&instance_mutex);
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+ list_add_tail(&mpcs->node, &mtk_pcs_lynxi_instances);
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+ mutex_unlock(&instance_mutex);
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+
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+ return 0;
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+}
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+
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+static int mtk_pcs_lynxi_remove(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct mtk_pcs_lynxi *cur, *tmp;
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+
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+ mutex_lock(&instance_mutex);
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+ list_for_each_entry_safe(cur, tmp, &mtk_pcs_lynxi_instances, node)
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+ if (cur->dev == dev) {
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+ list_del(&cur->node);
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+ kfree(cur);
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+ break;
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+ }
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+ mutex_unlock(&instance_mutex);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id mtk_pcs_lynxi_of_match[] = {
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+ { .compatible = "mediatek,mt7988-sgmii", .data = (void *)MTK_NETSYS_V3_AMA_RGC3 },
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+ { /* sentinel */ },
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+};
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+MODULE_DEVICE_TABLE(of, mtk_pcs_lynxi_of_match);
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+
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+struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np)
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+{
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+ struct platform_device *pdev;
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+ struct mtk_pcs_lynxi *mpcs;
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+
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+ if (!np)
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+ return NULL;
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+
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+ if (!of_device_is_available(np))
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+ return ERR_PTR(-ENODEV);
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+
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+ if (!of_match_node(mtk_pcs_lynxi_of_match, np))
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+ return ERR_PTR(-EINVAL);
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+
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+ pdev = of_find_device_by_node(np);
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+ if (!pdev || !platform_get_drvdata(pdev)) {
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+ if (pdev)
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+ put_device(&pdev->dev);
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+ return ERR_PTR(-EPROBE_DEFER);
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+ }
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+
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+ mpcs = platform_get_drvdata(pdev);
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+ device_link_add(dev, mpcs->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
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+
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+ return &mpcs->pcs;
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+}
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+EXPORT_SYMBOL(mtk_pcs_lynxi_get);
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+
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+void mtk_pcs_lynxi_put(struct phylink_pcs *pcs)
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+{
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+ struct mtk_pcs_lynxi *cur, *mpcs = NULL;
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+
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+ if (!pcs)
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+ return;
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+
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+ mutex_lock(&instance_mutex);
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+ list_for_each_entry(cur, &mtk_pcs_lynxi_instances, node)
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+ if (pcs == &cur->pcs) {
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+ mpcs = cur;
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+ break;
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+ }
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+ mutex_unlock(&instance_mutex);
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+
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+ if (WARN_ON(!mpcs))
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+ return;
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+
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+ put_device(mpcs->dev);
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+}
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+EXPORT_SYMBOL(mtk_pcs_lynxi_put);
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+
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+static struct platform_driver mtk_pcs_lynxi_driver = {
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+ .driver = {
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+ .name = "mtk-pcs-lynxi",
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+ .suppress_bind_attrs = true,
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+ .of_match_table = mtk_pcs_lynxi_of_match,
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+ },
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+ .probe = mtk_pcs_lynxi_probe,
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+ .remove = mtk_pcs_lynxi_remove,
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+};
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+module_platform_driver(mtk_pcs_lynxi_driver);
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+
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+MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
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+MODULE_DESCRIPTION("MediaTek LynxI HSGMII PCS");
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MODULE_LICENSE("GPL");
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--- a/include/linux/pcs/pcs-mtk-lynxi.h
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+++ b/include/linux/pcs/pcs-mtk-lynxi.h
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@@ -10,4 +10,15 @@ struct phylink_pcs *mtk_pcs_lynxi_create
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struct regmap *regmap,
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u32 ana_rgc3, u32 flags);
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void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs);
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+
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+#if IS_ENABLED(CONFIG_PCS_MTK_LYNXI)
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+struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np);
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+void mtk_pcs_lynxi_put(struct phylink_pcs *pcs);
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+#else
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+static inline struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np)
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+{
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+ return NULL;
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+}
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+static inline void mtk_pcs_lynxi_put(struct phylink_pcs *pcs) { }
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+#endif /* IS_ENABLED(CONFIG_PCS_MTK_LYNXI) */
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#endif
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