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f4c5d0e77e
Cherry-pick patches to support building RP1 modules. Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/17233 Signed-off-by: Robert Marko <robimarko@gmail.com> (cherry picked from commit 613dd79d5eabe53f07a7b74cc062d91cfc550403)
45 lines
1.3 KiB
Diff
45 lines
1.3 KiB
Diff
From d4e41ed9954fa86c4774f98d393aa401c81a68e7 Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Wed, 13 Nov 2024 13:10:27 +0000
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Subject: [PATCH 1427/1482] clk: rp1: Add RP1_CLK_DMA.
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The DMA block has a clock, but wasn't defined in the driver. This
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resulted in the parent being disabled as unused, and then DMA
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stopped working.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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drivers/clk/clk-rp1.c | 21 +++++++++++++++++++++
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1 file changed, 21 insertions(+)
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--- a/drivers/clk/clk-rp1.c
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+++ b/drivers/clk/clk-rp1.c
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@@ -1874,6 +1874,27 @@ static const struct rp1_clk_desc clk_des
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.flags = CLK_IS_CRITICAL,
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),
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+ [RP1_CLK_DMA] = REGISTER_CLK(
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+ .name = "clk_dma",
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+ .parents = {"pll_sys_pri_ph",
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+ "pll_video",
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+ "xosc",
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+ "clksrc_gp0",
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+ "clksrc_gp1",
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+ "clksrc_gp2",
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+ "clksrc_gp3",
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+ "clksrc_gp4",
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+ "clksrc_gp5"},
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+ .num_std_parents = 0,
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+ .num_aux_parents = 9,
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+ .ctrl_reg = CLK_DMA_CTRL,
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+ .div_int_reg = CLK_DMA_DIV_INT,
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+ .sel_reg = CLK_DMA_SEL,
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+ .div_int_max = DIV_INT_8BIT_MAX,
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+ .max_freq = 100 * MHz,
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+ .fc0_src = FC_NUM(2, 2),
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+ ),
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+
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[RP1_CLK_UART] = REGISTER_CLK(
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.name = "clk_uart",
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.parents = {"pll_sys_pri_ph",
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