openwrt/target/linux/bcm27xx/patches-6.6/950-1426-dt-arm64-Fixup-RP1-ethernet-DT-configuration.patch
John Audia f4c5d0e77e bcm27xx: patches: cherry-pick for RP1 kmods
Cherry-pick patches to support building RP1 modules.

Signed-off-by: John Audia <therealgraysky@proton.me>
Link: https://github.com/openwrt/openwrt/pull/17233
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 613dd79d5eabe53f07a7b74cc062d91cfc550403)
2024-12-28 14:11:52 +01:00

51 lines
1.9 KiB
Diff

From 0b4af929b7125abd3a262577b380c7c81ee9b1c5 Mon Sep 17 00:00:00 2001
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
Date: Mon, 11 Nov 2024 15:18:14 +0000
Subject: [PATCH 1426/1482] dt: arm64: Fixup RP1 ethernet DT configuration
Configure RP1's ethernet block to do the correct thing.
clk_eth is intended to be fixed at 125MHz, so use a new compatible,
and use assigned-clocks to configure the clock appropriately.
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
---
arch/arm64/boot/dts/broadcom/rp1.dtsi | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
--- a/arch/arm64/boot/dts/broadcom/rp1.dtsi
+++ b/arch/arm64/boot/dts/broadcom/rp1.dtsi
@@ -24,6 +24,7 @@
// RP1_PLL_VIDEO_CORE and dividers are now managed by VEC,DPI drivers
<&rp1_clocks RP1_PLL_SYS>,
<&rp1_clocks RP1_PLL_SYS_SEC>,
+ <&rp1_clocks RP1_CLK_ETH>,
<&rp1_clocks RP1_PLL_AUDIO>,
<&rp1_clocks RP1_PLL_AUDIO_SEC>,
<&rp1_clocks RP1_CLK_SYS>,
@@ -38,6 +39,7 @@
<1536000000>, // RP1_PLL_AUDIO_CORE
<200000000>, // RP1_PLL_SYS
<125000000>, // RP1_PLL_SYS_SEC
+ <125000000>, // RP1_CLK_ETH
<61440000>, // RP1_PLL_AUDIO
<192000000>, // RP1_PLL_AUDIO_SEC
<200000000>, // RP1_CLK_SYS
@@ -968,12 +970,14 @@
rp1_eth: ethernet@100000 {
reg = <0xc0 0x40100000 0x0 0x4000>;
- compatible = "cdns,macb";
+ compatible = "raspberrypi,rp1-gem", "cdns,macb";
#address-cells = <1>;
#size-cells = <0>;
interrupts = <RP1_INT_ETH IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&macb_pclk &macb_hclk &rp1_clocks RP1_CLK_ETH_TSU>;
- clock-names = "pclk", "hclk", "tsu_clk";
+ clocks = <&macb_pclk &macb_hclk
+ &rp1_clocks RP1_CLK_ETH_TSU
+ &rp1_clocks RP1_CLK_ETH>;
+ clock-names = "pclk", "hclk", "tsu_clk", "tx_clk";
phy-mode = "rgmii-id";
cdns,aw2w-max-pipe = /bits/ 8 <8>;
cdns,ar2r-max-pipe = /bits/ 8 <8>;