mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 14:13:16 +00:00
ed1536e0b6
Deleted (upstreamed): generic/backport-5.15/890-v5.19-net-sfp-Add-tx-fault-workaround-for-Huawei-MA5671A-SFP-ON.patch [1] Other patches automatically rebased. [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.41&id=99858114a3b2c8f5f8707d9bbd46c50f547c87c0 Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com>
88 lines
2.5 KiB
Diff
88 lines
2.5 KiB
Diff
From 60b7ddb0b3c9d906a20d8a84e527ccf5a792a64b Mon Sep 17 00:00:00 2001
|
|
From: Maxime Ripard <maxime@cerno.tech>
|
|
Date: Thu, 2 Dec 2021 17:04:18 +0100
|
|
Subject: [PATCH] drm/vc4: hdmi: Move clock calculation into its own
|
|
function
|
|
|
|
The code to compute our clock rate for a given setup will be called in
|
|
multiple places in the next patches, so let's create a separate function
|
|
for it.
|
|
|
|
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_hdmi.c | 49 +++++++++++++++++++++++-----------
|
|
1 file changed, 34 insertions(+), 15 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
|
|
@@ -1264,6 +1264,35 @@ vc4_hdmi_encoder_clock_valid(const struc
|
|
return MODE_OK;
|
|
}
|
|
|
|
+static unsigned long long
|
|
+vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
|
|
+ unsigned int bpc)
|
|
+{
|
|
+ unsigned long long clock = mode->crtc_clock * 1000;
|
|
+
|
|
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
|
|
+ clock = clock * 2;
|
|
+
|
|
+ return clock * bpc / 8;
|
|
+}
|
|
+
|
|
+static int
|
|
+vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
|
|
+ struct vc4_hdmi_connector_state *vc4_state,
|
|
+ const struct drm_display_mode *mode,
|
|
+ unsigned int bpc)
|
|
+{
|
|
+ unsigned long long clock;
|
|
+
|
|
+ clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc);
|
|
+ if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
|
|
+ return -EINVAL;
|
|
+
|
|
+ vc4_state->pixel_rate = clock;
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
|
|
#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
|
|
|
|
@@ -1276,6 +1305,7 @@ static int vc4_hdmi_encoder_atomic_check
|
|
struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
|
|
unsigned long long pixel_rate = mode->clock * 1000;
|
|
unsigned long long tmds_rate;
|
|
+ int ret;
|
|
|
|
if (vc4_hdmi->variant->unsupported_odd_h_timings &&
|
|
!(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
|
|
@@ -1297,21 +1327,10 @@ static int vc4_hdmi_encoder_atomic_check
|
|
pixel_rate = mode->clock * 1000;
|
|
}
|
|
|
|
- if (conn_state->max_bpc == 12) {
|
|
- pixel_rate = pixel_rate * 150;
|
|
- do_div(pixel_rate, 100);
|
|
- } else if (conn_state->max_bpc == 10) {
|
|
- pixel_rate = pixel_rate * 125;
|
|
- do_div(pixel_rate, 100);
|
|
- }
|
|
-
|
|
- if (mode->flags & DRM_MODE_FLAG_DBLCLK)
|
|
- pixel_rate = pixel_rate * 2;
|
|
-
|
|
- if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, pixel_rate) != MODE_OK)
|
|
- return -EINVAL;
|
|
-
|
|
- vc4_state->pixel_rate = pixel_rate;
|
|
+ ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, mode,
|
|
+ conn_state->max_bpc);
|
|
+ if (ret)
|
|
+ return ret;
|
|
|
|
return 0;
|
|
}
|