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16ae56b4f9
GPIOs > 31 require special handling. This patch fixes both the initialisation and direction get/set operations. Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Sander Vanheule <sander@svanheule.net>
341 lines
7.9 KiB
C
341 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/gpio/driver.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <asm/mach-rtl838x/mach-rtl83xx.h>
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/* RTL8231 registers for LED control */
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#define RTL8231_LED_FUNC0 0x0000
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#define RTL8231_GPIO_PIN_SEL(gpio) ((0x0002) + ((gpio) >> 4))
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#define RTL8231_GPIO_DIR(gpio) ((0x0005) + ((gpio) >> 4))
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#define RTL8231_GPIO_DATA(gpio) ((0x001C) + ((gpio) >> 4))
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#define USEC_TIMEOUT 5000
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struct rtl8231_gpios {
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struct gpio_chip gc;
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struct device *dev;
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u32 id;
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int smi_bus_id;
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u16 reg_shadow[0x20];
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u32 reg_cached;
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int ext_gpio_indrt_access;
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};
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extern struct mutex smi_lock;
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extern struct rtl83xx_soc_info soc_info;
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static u32 rtl8231_read(struct rtl8231_gpios *gpios, u32 reg)
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{
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u32 t = 0, n = 0;
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u8 bus_id = gpios->smi_bus_id;
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reg &= 0x1f;
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bus_id &= 0x1f;
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/* Calculate read register address */
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t = (bus_id << 2) | (reg << 7);
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/* Set execution bit: cleared when operation completed */
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t |= 1;
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// Start execution
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sw_w32(t, gpios->ext_gpio_indrt_access);
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do {
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udelay(1);
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t = sw_r32(gpios->ext_gpio_indrt_access);
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n++;
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} while ((t & 1) && (n < USEC_TIMEOUT));
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if (n >= USEC_TIMEOUT)
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return 0x80000000;
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pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, (t & 0xffff0000) >> 16);
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return (t & 0xffff0000) >> 16;
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}
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static int rtl8231_write(struct rtl8231_gpios *gpios, u32 reg, u32 data)
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{
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u32 t = 0, n = 0;
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u8 bus_id = gpios->smi_bus_id;
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pr_debug("%s: %x, %x, %x\n", __func__, bus_id, reg, data);
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reg &= 0x1f;
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bus_id &= 0x1f;
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t = (bus_id << 2) | (reg << 7) | (data << 16);
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/* Set write bit */
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t |= 2;
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/* Set execution bit: cleared when operation completed */
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t |= 1;
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// Start execution
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sw_w32(t, gpios->ext_gpio_indrt_access);
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do {
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udelay(1);
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t = sw_r32(gpios->ext_gpio_indrt_access);
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} while ((t & 1) && (n < USEC_TIMEOUT));
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if (n >= USEC_TIMEOUT)
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return -1;
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return 0;
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}
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static u32 rtl8231_read_cached(struct rtl8231_gpios *gpios, u32 reg)
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{
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if (reg > 0x1f)
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return 0;
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if (gpios->reg_cached & (1 << reg))
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return gpios->reg_shadow[reg];
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return rtl8231_read(gpios, reg);
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}
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/* Set Direction of the RTL8231 pin:
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* dir 1: input
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* dir 0: output
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*/
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static int rtl8231_pin_dir(struct rtl8231_gpios *gpios, u32 gpio, u32 dir)
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{
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u32 v;
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int pin_sel_addr = RTL8231_GPIO_PIN_SEL(gpio);
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int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
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int dpin = gpio % 16;
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if (gpio > 31) {
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pr_debug("WARNING: HIGH pin\n");
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dpin += 5;
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pin_dir_addr = pin_sel_addr;
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}
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v = rtl8231_read_cached(gpios, pin_dir_addr);
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if (v & 0x80000000) {
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pr_err("Error reading RTL8231\n");
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return -1;
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}
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v = (v & ~(1 << dpin)) | (dir << dpin);
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rtl8231_write(gpios, pin_dir_addr, v);
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gpios->reg_shadow[pin_dir_addr] = v;
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gpios->reg_cached |= 1 << pin_dir_addr;
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return 0;
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}
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static int rtl8231_pin_dir_get(struct rtl8231_gpios *gpios, u32 gpio, u32 *dir)
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{
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/* dir 1: input
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* dir 0: output
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*/
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u32 v;
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int pin_dir_addr = RTL8231_GPIO_DIR(gpio);
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int pin = gpio % 16;
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if (gpio > 31) {
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pin_dir_addr = RTL8231_GPIO_PIN_SEL(gpio);
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pin += 5;
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}
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v = rtl8231_read(gpios, pin_dir_addr);
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if (v & (1 << pin))
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*dir = 1;
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else
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*dir = 0;
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return 0;
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}
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static int rtl8231_pin_set(struct rtl8231_gpios *gpios, u32 gpio, u32 data)
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{
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u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));
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pr_debug("%s: %d to %d\n", __func__, gpio, data);
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if (v & 0x80000000) {
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pr_err("Error reading RTL8231\n");
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return -1;
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}
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v = (v & ~(1 << (gpio % 16))) | (data << (gpio % 16));
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rtl8231_write(gpios, RTL8231_GPIO_DATA(gpio), v);
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gpios->reg_shadow[RTL8231_GPIO_DATA(gpio)] = v;
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gpios->reg_cached |= 1 << RTL8231_GPIO_DATA(gpio);
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return 0;
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}
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static int rtl8231_pin_get(struct rtl8231_gpios *gpios, u32 gpio, u16 *state)
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{
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u32 v = rtl8231_read(gpios, RTL8231_GPIO_DATA(gpio));
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if (v & 0x80000000) {
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pr_err("Error reading RTL8231\n");
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return -1;
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}
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*state = v & 0xffff;
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return 0;
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}
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static int rtl8231_direction_input(struct gpio_chip *gc, unsigned int offset)
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{
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int err;
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struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
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pr_debug("%s: %d\n", __func__, offset);
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mutex_lock(&smi_lock);
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err = rtl8231_pin_dir(gpios, offset, 1);
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mutex_unlock(&smi_lock);
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return err;
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}
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static int rtl8231_direction_output(struct gpio_chip *gc, unsigned int offset, int value)
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{
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int err;
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struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
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pr_debug("%s: %d\n", __func__, offset);
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mutex_lock(&smi_lock);
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err = rtl8231_pin_dir(gpios, offset, 0);
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mutex_unlock(&smi_lock);
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if (!err)
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err = rtl8231_pin_set(gpios, offset, value);
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return err;
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}
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static int rtl8231_get_direction(struct gpio_chip *gc, unsigned int offset)
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{
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u32 v = 0;
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struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
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pr_debug("%s: %d\n", __func__, offset);
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mutex_lock(&smi_lock);
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rtl8231_pin_dir_get(gpios, offset, &v);
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mutex_unlock(&smi_lock);
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return v;
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}
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static int rtl8231_gpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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u16 state = 0;
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struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
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mutex_lock(&smi_lock);
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rtl8231_pin_get(gpios, offset, &state);
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mutex_unlock(&smi_lock);
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if (state & (1 << (offset % 16)))
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return 1;
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return 0;
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}
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void rtl8231_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
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{
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struct rtl8231_gpios *gpios = gpiochip_get_data(gc);
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rtl8231_pin_set(gpios, offset, value);
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}
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int rtl8231_init(struct rtl8231_gpios *gpios)
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{
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u32 v;
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pr_info("%s called, MDIO bus ID: %d\n", __func__, gpios->smi_bus_id);
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gpios->reg_cached = 0;
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if (soc_info.family == RTL8390_FAMILY_ID) {
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// RTL8390: Enable external gpio in global led control register
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sw_w32_mask(0x7 << 18, 0x4 << 18, RTL839X_LED_GLB_CTRL);
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} else if (soc_info.family == RTL8380_FAMILY_ID) {
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// RTL8380: Enable RTL8231 indirect access mode
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sw_w32_mask(0, 1, RTL838X_EXTRA_GPIO_CTRL);
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sw_w32_mask(3, 1, RTL838X_DMY_REG5);
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}
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/* Select GPIO functionality for pins 0-34 */
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rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(0), 0xffff);
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rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(16), 0xffff);
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v = rtl8231_read(gpios, RTL8231_GPIO_PIN_SEL(32));
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rtl8231_write(gpios, RTL8231_GPIO_PIN_SEL(32), v | 0x7);
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return 0;
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}
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static const struct of_device_id rtl8231_gpio_of_match[] = {
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{ .compatible = "realtek,rtl8231-gpio" },
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{},
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};
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MODULE_DEVICE_TABLE(of, rtl8231_gpio_of_match);
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static int rtl8231_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct rtl8231_gpios *gpios;
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int err;
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u32 indirect_bus_id;
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pr_info("Probing RTL8231 GPIOs\n");
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if (!np) {
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dev_err(&pdev->dev, "No DT found\n");
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return -EINVAL;
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}
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gpios = devm_kzalloc(dev, sizeof(*gpios), GFP_KERNEL);
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if (!gpios)
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return -ENOMEM;
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gpios->id = soc_info.id;
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if (soc_info.family == RTL8380_FAMILY_ID) {
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gpios->ext_gpio_indrt_access = RTL838X_EXT_GPIO_INDRT_ACCESS;
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}
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if (soc_info.family == RTL8390_FAMILY_ID) {
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gpios->ext_gpio_indrt_access = RTL839X_EXT_GPIO_INDRT_ACCESS;
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}
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/*
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* We use a default MDIO bus ID for the 8231 of 0, which can be overriden
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* by the indirect-access-bus-id property in the dts.
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*/
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gpios->smi_bus_id = 0;
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of_property_read_u32(np, "indirect-access-bus-id", &indirect_bus_id);
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gpios->smi_bus_id = indirect_bus_id;
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rtl8231_init(gpios);
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gpios->dev = dev;
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gpios->gc.base = 160;
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gpios->gc.ngpio = 36;
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gpios->gc.label = "rtl8231";
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gpios->gc.parent = dev;
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gpios->gc.owner = THIS_MODULE;
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gpios->gc.can_sleep = true;
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gpios->gc.direction_input = rtl8231_direction_input;
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gpios->gc.direction_output = rtl8231_direction_output;
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gpios->gc.set = rtl8231_gpio_set;
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gpios->gc.get = rtl8231_gpio_get;
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gpios->gc.get_direction = rtl8231_get_direction;
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err = devm_gpiochip_add_data(dev, &gpios->gc, gpios);
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return err;
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}
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static struct platform_driver rtl8231_gpio_driver = {
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.driver = {
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.name = "rtl8231-gpio",
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.of_match_table = rtl8231_gpio_of_match,
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},
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.probe = rtl8231_gpio_probe,
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};
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module_platform_driver(rtl8231_gpio_driver);
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MODULE_DESCRIPTION("Realtek RTL8231 GPIO expansion chip support");
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MODULE_LICENSE("GPL v2");
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