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c6ddf8d502
Many changes were done in drivers/pinctrl/bcm/pinctrl-bcm2835.c between
5.4.171 and 5.4.179.
The following 3 patches do not apply any more:
* target/linux/bcm27xx/patches-5.4/950-0316-pinctrl-bcm2835-Add-support-for-BCM2711-pull-up-func.patch
This was already integrated in kernel v5.4-rc1, it was never needed.
* target/linux/bcm27xx/patches-5.4/950-0328-Revert-pinctrl-bcm2835-Pass-irqchip-when-adding-gpio.patch
* target/linux/bcm27xx/patches-5.4/950-0362-pinctrl-bcm2835-Change-init-order-for-gpio-hogs.patch
I think these were done to fix the problem which was really fixed in
commit 75278f1aff5e ("pinctrl: bcm2835: Change init order for gpio
hogs") from v5.4.175
target/linux/generic/backport-5.4/716-v5.5-net-sfp-move-fwnode-parsing-into-sfp-bus-layer.patch
Move fwnode_device_is_available to the same position as in kernel 5.10.
target/linux/layerscape/patches-5.4/302-dts-0083-arm64-ls1028a-qds-correct-bus-of-rtc.patch
Applied in commit 65816c1034769e714edb70f59a33bc5472d9e55f ("arm64: dts:
ls1028a-qds: move rtc node to the correct i2c bus")
Compile-tested: lantiq/xrx200, bcm27xx/bcm2710
Run-tested: lantiq/xrx200
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
60 lines
1.9 KiB
Diff
60 lines
1.9 KiB
Diff
From d0ff7a1bcfe886cab1a237895b08ac51ecfe10e7 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Wed, 10 Apr 2019 08:00:47 -0700
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Subject: [PATCH 04/12] PCI: add quirk for Gateworks PLX PEX860x switch with
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GPIO PERST#
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Gateworks boards use PLX PEX860x switches where downstream ports
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have their PERST# driven from the PEX GPIO.
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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---
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drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++
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1 file changed, 32 insertions(+)
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--- a/drivers/pci/quirks.c
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+++ b/drivers/pci/quirks.c
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@@ -25,6 +25,7 @@
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#include <linux/ktime.h>
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#include <linux/mm.h>
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#include <linux/nvme.h>
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+#include <linux/of.h>
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#include <linux/platform_data/x86/apple.h>
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#include <linux/pm_runtime.h>
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#include <linux/suspend.h>
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@@ -5793,3 +5794,34 @@ static void nvidia_ion_ahci_fixup(struct
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pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING;
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup);
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+
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+#ifdef CONFIG_PCI_HOST_THUNDER_PEM
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+/*
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+ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
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+ * as they are used for slots1-7 PERST#
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+ */
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+static void newport_pciesw_early_fixup(struct pci_dev *dev)
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+{
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+ u32 dw;
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+
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+ if (!of_machine_is_compatible("gw,newport"))
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+ return;
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+
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+ if (dev->devfn != 0)
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+ return;
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+
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+ dev_info(&dev->dev, "de-asserting PERST#\n");
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+ pci_read_config_dword(dev, 0x62c, &dw);
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+ dw |= 0xaaa8; /* GPIO1-7 outputs */
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+ pci_write_config_dword(dev, 0x62c, dw);
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+
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+ pci_read_config_dword(dev, 0x644, &dw);
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+ dw |= 0xfe; /* GPIO1-7 output high */
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+ pci_write_config_dword(dev, 0x644, dw);
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+
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+ msleep(100);
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+}
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, newport_pciesw_early_fixup);
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, newport_pciesw_early_fixup);
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, newport_pciesw_early_fixup);
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+#endif /* CONFIG_PCI_HOST_THUNDER_PEM */
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