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ee6ba216d8
Fix FDB learning bugs when VLAN filtering is enabled. Signed-off-by: DENG Qingfang <dqfext@gmail.com> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com> Tested-by: Stijn Tintel <stijn@linux-ipv6.be>
263 lines
9.2 KiB
Diff
263 lines
9.2 KiB
Diff
From e3a402764c5753698e7a9e45d4d21f093faa7852 Mon Sep 17 00:00:00 2001
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From: DENG Qingfang <dqfext@gmail.com>
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Date: Wed, 4 Aug 2021 00:04:02 +0800
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Subject: [PATCH] net: dsa: mt7530: use independent VLAN learning on
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VLAN-unaware bridges
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Consider the following bridge configuration, where bond0 is not
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offloaded:
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+-- br0 --+
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/ / | \
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/ / | \
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/ | | bond0
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/ | | / \
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swp0 swp1 swp2 swp3 swp4
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. . .
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. . .
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A B C
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Ideally, when the switch receives a packet from swp3 or swp4, it should
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forward the packet to the CPU, according to the port matrix and unknown
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unicast flood settings.
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But packet loss will happen if the destination address is at one of the
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offloaded ports (swp0~2). For example, when client C sends a packet to
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A, the FDB lookup will indicate that it should be forwarded to swp0, but
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the port matrix of swp3 and swp4 is configured to only allow the CPU to
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be its destination, so it is dropped.
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However, this issue does not happen if the bridge is VLAN-aware. That is
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because VLAN-aware bridges use independent VLAN learning, i.e. use VID
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for FDB lookup, on offloaded ports. As swp3 and swp4 are not offloaded,
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shared VLAN learning with default filter ID of 0 is used instead. So the
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lookup for A with filter ID 0 never hits and the packet can be forwarded
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to the CPU.
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In the current code, only two combinations were used to toggle user
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ports' VLAN awareness: one is PCR.PORT_VLAN set to port matrix mode with
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PVC.VLAN_ATTR set to transparent port, the other is PCR.PORT_VLAN set to
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security mode with PVC.VLAN_ATTR set to user port.
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It turns out that only PVC.VLAN_ATTR contributes to VLAN awareness, and
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port matrix mode just skips the VLAN table lookup. The reference manual
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is somehow misleading when describing PORT_VLAN modes. It states that
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PORT_MEM (VLAN port member) is used for destination if the VLAN table
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lookup hits, but actually **PORT_MEM & PORT_MATRIX** (bitwise AND of
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VLAN port member and port matrix) is used instead, which means we can
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have two or more separate VLAN-aware bridges with the same PVID and
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traffic won't leak between them.
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Therefore, to solve this, enable independent VLAN learning with PVID 0
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on VLAN-unaware bridges, by setting their PCR.PORT_VLAN to fallback
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mode, while leaving standalone ports in port matrix mode. The CPU port
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is always set to fallback mode to serve those bridges.
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During testing, it is found that FDB lookup with filter ID of 0 will
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also hit entries with VID 0 even with independent VLAN learning. To
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avoid that, install all VLANs with filter ID of 1.
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Signed-off-by: DENG Qingfang <dqfext@gmail.com>
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Reviewed-by: Vladimir Oltean <olteanv@gmail.com>
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Signed-off-by: David S. Miller <davem@davemloft.net>
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---
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drivers/net/dsa/mt7530.c | 72 +++++++++++++++++++++++++++++-----------
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drivers/net/dsa/mt7530.h | 9 ++++-
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2 files changed, 60 insertions(+), 21 deletions(-)
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--- a/drivers/net/dsa/mt7530.c
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+++ b/drivers/net/dsa/mt7530.c
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@@ -1011,6 +1011,10 @@ mt753x_cpu_port_enable(struct dsa_switch
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mt7530_write(priv, MT7530_PCR_P(port),
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PCR_MATRIX(dsa_user_ports(priv->ds)));
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+ /* Set to fallback mode for independent VLAN learning */
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+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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+ MT7530_PORT_FALLBACK_MODE);
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+
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return 0;
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}
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@@ -1165,6 +1169,10 @@ mt7530_port_bridge_join(struct dsa_switc
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mt7530_clear(priv, MT7530_PSC_P(port), SA_DIS);
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+ /* Set to fallback mode for independent VLAN learning */
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+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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+ MT7530_PORT_FALLBACK_MODE);
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+
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mutex_unlock(&priv->reg_mutex);
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return 0;
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@@ -1177,16 +1185,21 @@ mt7530_port_set_vlan_unaware(struct dsa_
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bool all_user_ports_removed = true;
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int i;
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- /* When a port is removed from the bridge, the port would be set up
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- * back to the default as is at initial boot which is a VLAN-unaware
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- * port.
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+ /* This is called after .port_bridge_leave when leaving a VLAN-aware
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+ * bridge. Don't set standalone ports to fallback mode.
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*/
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- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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- MT7530_PORT_MATRIX_MODE);
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+ if (dsa_to_port(ds, port)->bridge_dev)
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+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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+ MT7530_PORT_FALLBACK_MODE);
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+
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mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
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VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
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PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
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+ /* Set PVID to 0 */
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+ mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
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+ G0_PORT_VID_DEF);
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+
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for (i = 0; i < MT7530_NUM_PORTS; i++) {
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if (dsa_is_user_port(ds, i) &&
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dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
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@@ -1212,15 +1225,14 @@ mt7530_port_set_vlan_aware(struct dsa_sw
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struct mt7530_priv *priv = ds->priv;
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/* Trapped into security mode allows packet forwarding through VLAN
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- * table lookup. CPU port is set to fallback mode to let untagged
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- * frames pass through.
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+ * table lookup.
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*/
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- if (dsa_is_cpu_port(ds, port))
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- mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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- MT7530_PORT_FALLBACK_MODE);
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- else
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+ if (dsa_is_user_port(ds, port)) {
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mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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MT7530_PORT_SECURITY_MODE);
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+ mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
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+ G0_PORT_VID(priv->ports[port].pvid));
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+ }
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/* Set the port as a user port which is to be able to recognize VID
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* from incoming packets before fetching entry within the VLAN table.
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@@ -1264,6 +1276,13 @@ mt7530_port_bridge_leave(struct dsa_swit
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mt7530_set(priv, MT7530_PSC_P(port), SA_DIS);
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+ /* When a port is removed from the bridge, the port would be set up
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+ * back to the default as is at initial boot which is a VLAN-unaware
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+ * port.
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+ */
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+ mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
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+ MT7530_PORT_MATRIX_MODE);
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+
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mutex_unlock(&priv->reg_mutex);
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}
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@@ -1406,7 +1425,8 @@ mt7530_hw_vlan_add(struct mt7530_priv *p
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/* Validate the entry with independent learning, create egress tag per
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* VLAN and joining the port as one of the port members.
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*/
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- val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
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+ val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
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+ VLAN_VALID;
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mt7530_write(priv, MT7530_VAWD1, val);
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/* Decide whether adding tag or not for those outgoing packets from the
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@@ -1499,9 +1519,13 @@ mt7530_port_vlan_add(struct dsa_switch *
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}
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if (pvid) {
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- mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
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- G0_PORT_VID(vlan->vid_end));
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priv->ports[port].pvid = vlan->vid_end;
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+
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+ /* Only configure PVID if VLAN filtering is enabled */
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+ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
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+ mt7530_rmw(priv, MT7530_PPBV1_P(port),
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+ G0_PORT_VID_MASK,
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+ G0_PORT_VID(vlan->vid_end));
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}
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mutex_unlock(&priv->reg_mutex);
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@@ -1513,11 +1537,10 @@ mt7530_port_vlan_del(struct dsa_switch *
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{
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struct mt7530_hw_vlan_entry target_entry;
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struct mt7530_priv *priv = ds->priv;
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- u16 vid, pvid;
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+ u16 vid;
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mutex_lock(&priv->reg_mutex);
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- pvid = priv->ports[port].pvid;
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for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
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mt7530_hw_vlan_entry_init(&target_entry, port, 0);
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mt7530_hw_vlan_update(priv, vid, &target_entry,
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@@ -1526,12 +1549,13 @@ mt7530_port_vlan_del(struct dsa_switch *
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/* PVID is being restored to the default whenever the PVID port
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* is being removed from the VLAN.
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*/
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- if (pvid == vid)
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- pvid = G0_PORT_VID_DEF;
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+ if (priv->ports[port].pvid == vid) {
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+ priv->ports[port].pvid = G0_PORT_VID_DEF;
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+ mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
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+ G0_PORT_VID_DEF);
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+ }
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}
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- mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
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- priv->ports[port].pvid = pvid;
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mutex_unlock(&priv->reg_mutex);
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@@ -1827,6 +1851,10 @@ mt7530_setup(struct dsa_switch *ds)
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return ret;
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} else {
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mt7530_port_disable(ds, i);
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+
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+ /* Set default PVID to 0 on all user ports */
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+ mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
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+ G0_PORT_VID_DEF);
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}
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/* Enable consistent egress tag */
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@@ -1993,6 +2021,10 @@ mt7531_setup(struct dsa_switch *ds)
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return ret;
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} else {
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mt7530_port_disable(ds, i);
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+
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+ /* Set default PVID to 0 on all user ports */
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+ mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK,
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+ G0_PORT_VID_DEF);
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}
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/* Enable consistent egress tag */
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--- a/drivers/net/dsa/mt7530.h
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+++ b/drivers/net/dsa/mt7530.h
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@@ -145,11 +145,18 @@ enum mt7530_vlan_cmd {
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#define VTAG_EN BIT(28)
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/* VLAN Member Control */
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#define PORT_MEM(x) (((x) & 0xff) << 16)
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+/* Filter ID */
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+#define FID(x) (((x) & 0x7) << 1)
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/* VLAN Entry Valid */
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#define VLAN_VALID BIT(0)
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#define PORT_MEM_SHFT 16
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#define PORT_MEM_MASK 0xff
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+enum mt7530_fid {
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+ FID_STANDALONE = 0,
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+ FID_BRIDGED = 1,
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+};
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+
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#define MT7530_VAWD2 0x98
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/* Egress Tag Control */
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#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
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@@ -244,7 +251,7 @@ enum mt7530_vlan_port_attr {
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#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
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#define G0_PORT_VID(x) (((x) & 0xfff) << 0)
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#define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
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-#define G0_PORT_VID_DEF G0_PORT_VID(1)
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+#define G0_PORT_VID_DEF G0_PORT_VID(0)
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/* Register for port MAC control register */
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#define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
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