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57 lines
1.7 KiB
Diff
57 lines
1.7 KiB
Diff
From fb143ba7f7cd215bc2fc34a478c4c0b6dc56e537 Mon Sep 17 00:00:00 2001
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From: Hauke Mehrtens <hauke@hauke-m.de>
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Date: Mon, 6 Jan 2014 14:51:59 +0100
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Subject: [PATCH] MIPS: BCM47XX: fix position of cpu_wait disabling
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The disabling of cpu_wait was done too early, before the detection was
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done. This moves the code to a position where it actually works.
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Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
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Acked-by: Rafa? Mi?ecki <zajec5@gmail.com>
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---
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arch/mips/bcm47xx/setup.c | 34 +++++++++++++++++++++++++---------
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1 file changed, 25 insertions(+), 9 deletions(-)
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--- a/arch/mips/bcm47xx/setup.c
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+++ b/arch/mips/bcm47xx/setup.c
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@@ -37,6 +37,7 @@
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#include <asm/prom.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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+#include <asm/idle.h>
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#include <bcm47xx.h>
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#include <bcm47xx_nvram.h>
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#include <bcm47xx_board.h>
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@@ -231,6 +232,31 @@ void __init plat_mem_setup(void)
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mips_set_machine_name(bcm47xx_board_get_name());
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}
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+static int __init bcm47xx_cpu_fixes(void)
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+{
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+ switch (bcm47xx_bus_type) {
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+#ifdef CONFIG_BCM47XX_SSB
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+ case BCM47XX_BUS_TYPE_SSB:
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+ /* Nothing to do */
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+ break;
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+#endif
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+#ifdef CONFIG_BCM47XX_BCMA
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+ case BCM47XX_BUS_TYPE_BCMA:
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+ /* The BCM4706 has a problem with the CPU wait instruction.
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+ * When r4k_wait or r4k_wait_irqoff is used will just hang and
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+ * not return from a msleep(). Removing the cpu_wait
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+ * functionality is a workaround for this problem. The BCM4716
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+ * does not have this problem.
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+ */
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+ if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706)
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+ cpu_wait = NULL;
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+ break;
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+#endif
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+ }
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+ return 0;
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+}
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+arch_initcall(bcm47xx_cpu_fixes);
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+
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static int __init bcm47xx_register_bus_complete(void)
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{
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switch (bcm47xx_bus_type) {
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