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30 lines
1022 B
Diff
30 lines
1022 B
Diff
From c4374e446b6957234432d5c3f5d5f89f1acb807d Mon Sep 17 00:00:00 2001
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From: popcornmix <popcornmix@gmail.com>
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Date: Thu, 7 Nov 2019 12:25:27 +0000
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Subject: [PATCH] fixup! clk-raspberrypi: Also support v3d clock
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---
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drivers/clk/bcm/clk-raspberrypi.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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--- a/drivers/clk/bcm/clk-raspberrypi.c
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+++ b/drivers/clk/bcm/clk-raspberrypi.c
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@@ -474,7 +474,7 @@ raspberrypi_register_pll_divider(struct
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* PLLH's channels have a fixed divide by 10 afterwards, which
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* is what our consumers are actually using.
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*/
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- if (data->fixed_divider != 1) {
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+ if (data->fixed_divider != 0) {
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struct clk_lookup *lookup;
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struct clk_hw *clk = clk_hw_register_fixed_factor(rpi->dev,
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data->divider_name,
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@@ -559,7 +559,7 @@ static const struct raspberrypi_clk_desc
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.source_pll = "osc",
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.divider_name = "pllb_arm",
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.lookup = "cpu0",
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- .fixed_divider = 2,
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+ .fixed_divider = 1,
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.clock_id = RPI_FIRMWARE_ARM_CLK_ID,
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.flags = CLK_SET_RATE_PARENT),
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};
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