mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-26 00:41:17 +00:00
3ea6125c50
Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide
direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO
bus the switch listens on. The PHY muxing feature makes use of this.
This is problematic as the PHY may be attached before the switch is
initialised, in which case, the PHY will fail to be attached.
Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration
of switch MDIO bus") on mainline Linux, we can describe the switch PHYs on
the MDIO bus of the switch on the device tree.
When the PHY is described this way, the switch will be initialised first,
then the switch MDIO bus will be registered. Only after these steps, the
PHY will be attached.
Describe the switch PHYs on mt7621.dtsi and remove defining the switch PHY
on the SoC's mdio bus node. When the PHY muxing is in use, the interrupts
for the muxed PHY won't work, therefore delete the "interrupts" property on
the devices where the PHY muxing feature is in use.
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
204 lines
3.3 KiB
Plaintext
204 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "mt7621.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/input/input.h>
|
|
#include <dt-bindings/leds/common.h>
|
|
|
|
/ {
|
|
compatible = "dlink,covr-x1860-a1", "mediatek,mt7621-soc";
|
|
model = "D-Link COVR-X1860 A1";
|
|
|
|
aliases {
|
|
led-boot = &status_orange;
|
|
led-failsafe = &status_red;
|
|
led-running = &status_white;
|
|
led-upgrade = &status_red;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "console=ttyS0,115200";
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
reset {
|
|
label = "reset";
|
|
linux,code = <KEY_RESTART>;
|
|
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wps {
|
|
label = "wps";
|
|
linux,code = <KEY_WPS_BUTTON>;
|
|
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
status_white: power {
|
|
function = LED_FUNCTION_STATUS;
|
|
color = <LED_COLOR_ID_WHITE>;
|
|
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
status_orange: status_orange {
|
|
function = LED_FUNCTION_STATUS;
|
|
color = <LED_COLOR_ID_ORANGE>;
|
|
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
|
|
default-state = "on";
|
|
};
|
|
|
|
status_red: status_red {
|
|
function = LED_FUNCTION_STATUS;
|
|
color = <LED_COLOR_ID_RED>;
|
|
gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
virtual_flash {
|
|
compatible = "mtd-concat";
|
|
|
|
devices = <&fwconcat0 &fwconcat1>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "ubi";
|
|
reg = <0x0 0x0>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&nand {
|
|
status = "okay";
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "bootloader";
|
|
reg = <0x0 0x80000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@80000 {
|
|
label = "config";
|
|
reg = <0x80000 0x80000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@100000 {
|
|
label = "factory";
|
|
reg = <0x100000 0x80000>;
|
|
read-only;
|
|
|
|
nvmem-layout {
|
|
compatible = "fixed-layout";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
eeprom_factory_0: eeprom@0 {
|
|
reg = <0x0 0xe00>;
|
|
};
|
|
|
|
precal_factory_e10: precal@e10 {
|
|
reg = <0xe10 0x19c10>;
|
|
};
|
|
};
|
|
};
|
|
|
|
partition@180000 {
|
|
label = "config2";
|
|
reg = <0x180000 0x40000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@1c0000 {
|
|
label = "kernel";
|
|
reg = <0x1c0000 0x800000>;
|
|
};
|
|
|
|
fwconcat0: partition@9c0000 {
|
|
label = "fwconcat0";
|
|
reg = <0x9c0000 0x2000000>;
|
|
};
|
|
|
|
partition@29c0000 {
|
|
label = "kernel2";
|
|
reg = <0x29c0000 0x800000>;
|
|
read-only;
|
|
};
|
|
|
|
fwconcat1: partition@31c0000 {
|
|
label = "fwconcat1";
|
|
reg = <0x31c0000 0x2a00000>;
|
|
};
|
|
|
|
partition@5bc0000 {
|
|
label = "private";
|
|
reg = <0x5bc0000 0x1400000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@6fc0000 {
|
|
label = "mydlink";
|
|
reg = <0x6fc0000 0x600000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@75c0000 {
|
|
label = "myconfig";
|
|
reg = <0x75c0000 0xa00000>;
|
|
read-only;
|
|
};
|
|
};
|
|
};
|
|
|
|
&pcie {
|
|
status = "okay";
|
|
};
|
|
|
|
&pcie1 {
|
|
wifi@0,0 {
|
|
compatible = "mediatek,mt76";
|
|
reg = <0x0000 0 0 0 0>;
|
|
nvmem-cells = <&eeprom_factory_0>, <&precal_factory_e10>;
|
|
nvmem-cell-names = "eeprom", "precal";
|
|
mediatek,disable-radar-background;
|
|
};
|
|
};
|
|
|
|
&gmac1 {
|
|
status = "okay";
|
|
phy-handle = <ðphy4>;
|
|
};
|
|
|
|
ðphy4 {
|
|
/delete-property/ interrupts;
|
|
};
|
|
|
|
&switch0 {
|
|
ports {
|
|
port@0 {
|
|
status = "okay";
|
|
label = "internet";
|
|
};
|
|
|
|
port@2 {
|
|
status = "okay";
|
|
label = "ethernet";
|
|
};
|
|
};
|
|
};
|