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550f71ec8d
RPM clock controller driver had made its way upstream and previous approach of directly redoing a driver to support ipq806x is a no go anymore. Thus reverting mentioned patches to upstream state and renaming in correct patch numbering accordance. To make the driver work on ipq806x boards we introduce a custom patch. Signed-off-by: Pavel Kubelun <be.dissent@gmail.com>
82 lines
3.1 KiB
Diff
82 lines
3.1 KiB
Diff
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
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+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
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@@ -12,6 +12,7 @@ Required properties :
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"qcom,rpmcc-msm8916", "qcom,rpmcc"
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"qcom,rpmcc-apq8064", "qcom,rpmcc"
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+ "qcom,rpmcc-ipq806x", "qcom,rpmcc"
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- #clock-cells : shall contain 1
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--- a/drivers/clk/qcom/clk-rpm.c
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+++ b/drivers/clk/qcom/clk-rpm.c
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@@ -359,6 +359,16 @@ DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a
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DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
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DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK);
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+/* ipq806x */
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+DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
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+DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
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+DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
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+DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
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+DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
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+DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
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+DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
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+DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
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+
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static struct clk_rpm *apq8064_clks[] = {
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[RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
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[RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
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@@ -380,13 +390,38 @@ static struct clk_rpm *apq8064_clks[] =
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[RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk,
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};
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+static struct clk_rpm *ipq806x_clks[] = {
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+ [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
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+ [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
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+ [RPM_CFPB_CLK] = &ipq806x_cfpb_clk,
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+ [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk,
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+ [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk,
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+ [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk,
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+ [RPM_EBI1_CLK] = &ipq806x_ebi1_clk,
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+ [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk,
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+ [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk,
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+ [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk,
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+ [RPM_SFPB_CLK] = &ipq806x_sfpb_clk,
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+ [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk,
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+ [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk,
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+ [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk,
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+ [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk,
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+ [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
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+};
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+
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static const struct rpm_clk_desc rpm_clk_apq8064 = {
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.clks = apq8064_clks,
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.num_clks = ARRAY_SIZE(apq8064_clks),
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};
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+static const struct rpm_clk_desc rpm_clk_ipq806x = {
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+ .clks = ipq806x_clks,
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+ .num_clks = ARRAY_SIZE(ipq806x_clks),
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+};
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+
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static const struct of_device_id rpm_clk_match_table[] = {
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{ .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
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+ { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
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{ }
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};
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MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
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--- a/include/dt-bindings/clock/qcom,rpmcc.h
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+++ b/include/dt-bindings/clock/qcom,rpmcc.h
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@@ -37,6 +37,10 @@
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#define RPM_SYS_FABRIC_A_CLK 19
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#define RPM_SFPB_CLK 20
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#define RPM_SFPB_A_CLK 21
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+#define RPM_NSS_FABRIC_0_CLK 22
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+#define RPM_NSS_FABRIC_0_A_CLK 23
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+#define RPM_NSS_FABRIC_1_CLK 24
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+#define RPM_NSS_FABRIC_1_A_CLK 25
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/* msm8916 */
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#define RPM_SMD_XO_CLK_SRC 0
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