openwrt/target/linux/ramips/dts/mt7620a_phicomm_psg1208.dts
Chuanhong Guo b756ea2a90 ramips: replace pinctrl property names
Upstream pinctrl driver in drivers/staging uses
groups/function/ralink,num-gpios instead of
ralink,group/ralink,function/ralink,nr-gpio
Replace these properties in dts as well as the pinctrl driver in
patches-4.14.
This commit is created using:
sed -i 's/ralink,group/groups/g'
sed -i 's/ralink,function/function/g'
sed -i 's/ralink,nr-gpio/ralink,num-gpios/g'

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
2020-04-12 22:29:17 +08:00

121 lines
1.8 KiB
Plaintext

/dts-v1/;
#include "mt7620a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
compatible = "phicomm,psg1208", "ralink,mt7620a-soc";
model = "Phicomm PSG1208";
aliases {
led-boot = &led_wps;
led-failsafe = &led_wps;
led-running = &led_wps;
led-upgrade = &led_wps;
};
leds {
compatible = "gpio-leds";
led_wps: wps {
label = "psg1208:white:wps";
gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
wlan {
label = "psg1208:white:wlan2g";
gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&gpio1 {
status = "okay";
};
&gpio3 {
status = "okay";
};
&spi0 {
status = "okay";
m25p80@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <10000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x0 0x30000>;
read-only;
};
partition@20000 {
label = "u-boot-env";
reg = <0x30000 0x10000>;
read-only;
};
factory: partition@30000 {
label = "factory";
reg = <0x40000 0x10000>;
read-only;
};
partition@40000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x50000 0x7b0000>;
};
};
};
};
&state_default {
gpio {
groups = "i2c", "spi refclk", "wled";
function = "gpio";
};
};
&ethernet {
pinctrl-names = "default";
pinctrl-0 = <&ephy_pins>;
mtd-mac-address = <&factory 0x4>;
mediatek,portmap = "llllw";
};
&pcie {
status = "okay";
};
&pcie0 {
mt76@0,0 {
reg = <0x0000 0 0 0 0>;
mediatek,mtd-eeprom = <&factory 0x8000>;
ieee80211-freq-limit = <5000000 6000000>;
};
};
&wmac {
ralink,mtd-eeprom = <&factory 0>;
};