mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-25 08:21:14 +00:00
da55758cc5
Specify the device_type property for PCI as well as PCIe controllers. Otherwise, the PCI range parser will not be selected when using kernel 5.10. Signed-off-by: David Bauer <mail@david-bauer.net>
355 lines
7.0 KiB
Plaintext
355 lines
7.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
|
|
#include "ath79.dtsi"
|
|
|
|
/ {
|
|
compatible = "qca,qca9550";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
chosen {
|
|
bootargs = "console=ttyS0,115200n8";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "mips,mips74Kc";
|
|
clocks = <&pll ATH79_CLK_CPU>;
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
extosc: ref {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-output-names = "ref";
|
|
clock-frequency = <40000000>;
|
|
};
|
|
|
|
ahb {
|
|
apb {
|
|
ddr_ctrl: memory-controller@18000000 {
|
|
compatible = "qca,qca9550-ddr-controller",
|
|
"qca,ar7240-ddr-controller";
|
|
reg = <0x18000000 0x100>;
|
|
|
|
#qca,ddr-wb-channel-cells = <1>;
|
|
};
|
|
|
|
uart: uart@18020000 {
|
|
compatible = "ns16550a";
|
|
reg = <0x18020000 0x20>;
|
|
|
|
interrupts = <3>;
|
|
|
|
clocks = <&pll ATH79_CLK_REF>;
|
|
clock-names = "uart";
|
|
|
|
reg-io-width = <4>;
|
|
reg-shift = <2>;
|
|
no-loopback-test;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_phy0: usb-phy0@18030000 {
|
|
compatible ="qca,qca9550-usb-phy", "qca,ar7200-usb-phy";
|
|
reg = <0x18030000 4>, <0x18030004 4>;
|
|
|
|
reset-names = "usb-phy", "usb-suspend-override";
|
|
resets = <&rst 4>, <&rst 3>;
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_phy1: usb-phy1@18030010 {
|
|
compatible = "qca,qca9550-usb-phy", "qca,ar7200-usb-phy";
|
|
reg = <0x18030010 4>, <0x18030014 4>;
|
|
|
|
reset-names = "usb-phy", "usb-suspend-override";
|
|
resets = <&rst2 4>, <&rst2 3>;
|
|
|
|
#phy-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio: gpio@18040000 {
|
|
compatible = "qca,qca9550-gpio",
|
|
"qca,ar9340-gpio";
|
|
reg = <0x18040000 0x28>;
|
|
|
|
interrupts = <2>;
|
|
ngpios = <24>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pinmux: pinmux@1804002c {
|
|
compatible = "pinctrl-single";
|
|
|
|
reg = <0x1804002c 0x44>;
|
|
|
|
#size-cells = <0>;
|
|
|
|
pinctrl-single,bit-per-mux;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0x1>;
|
|
#pinctrl-cells = <2>;
|
|
|
|
jtag_disable_pins: pinmux_jtag_disable_pins {
|
|
pinctrl-single,bits = <0x40 0x2 0x2>;
|
|
};
|
|
};
|
|
|
|
pll: pll-controller@18050000 {
|
|
compatible = "qca,qca9550-pll",
|
|
"qca,qca9550-pll", "syscon";
|
|
reg = <0x18050000 0x50>;
|
|
|
|
#clock-cells = <1>;
|
|
clock-output-names = "cpu", "ddr", "ahb";
|
|
|
|
clocks = <&extosc>;
|
|
};
|
|
|
|
wdt: wdt@18060008 {
|
|
compatible = "qca,ar7130-wdt";
|
|
reg = <0x18060008 0x8>;
|
|
|
|
interrupts = <4>;
|
|
|
|
clocks = <&pll ATH79_CLK_AHB>;
|
|
clock-names = "wdt";
|
|
};
|
|
|
|
rst: reset-controller@1806001c {
|
|
compatible = "qca,qca9550-reset",
|
|
"qca,ar7100-reset";
|
|
reg = <0x1806001c 0x4>;
|
|
|
|
#reset-cells = <1>;
|
|
interrupt-parent = <&cpuintc>;
|
|
|
|
intc2: interrupt-controller2 {
|
|
compatible = "qca,ar9340-intc";
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
qca,int-status-addr = <0xac>;
|
|
qca,pending-bits = <0xf>, /* wmac */
|
|
<0x1f0>; /* pcie rc 0 */
|
|
};
|
|
|
|
intc3: interrupt-controller3 {
|
|
compatible = "qca,ar9340-intc";
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <3>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
qca,int-status-addr = <0xac>;
|
|
qca,pending-bits = <0x1f000>, /* pcie rc 1 */
|
|
<0x1000000>, /* usb1 */
|
|
<0x10000000>; /* usb2 */
|
|
};
|
|
};
|
|
|
|
rst2: reset-controller@180600c0 {
|
|
compatible = "qca,qca9550-reset",
|
|
"qca,ar7100-reset",
|
|
"simple-bus";
|
|
reg = <0x180600c0 0x4>;
|
|
|
|
#reset-cells = <1>;
|
|
};
|
|
};
|
|
|
|
gmac: gmac@18070000 {
|
|
compatible = "qca,qca9550-gmac";
|
|
reg = <0x18070000 0x58>;
|
|
};
|
|
|
|
pcie0: pcie-controller@180c0000 {
|
|
compatible = "qcom,qca9550-pci", "qcom,ar7240-pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x0 0x0>;
|
|
reg = <0x180c0000 0x1000>, /* CRP */
|
|
<0x180f0000 0x100>, /* CTRL */
|
|
<0x14000000 0x1000>; /* CFG */
|
|
reg-names = "crp_base", "ctrl_base", "cfg_base";
|
|
ranges = <0x2000000 0 0x10000000 0x10000000 0 0x02000000 /* pci memory */
|
|
0x1000000 0 0x00000000 0x0000000 0 0x000001>; /* io space */
|
|
interrupt-parent = <&intc2>;
|
|
interrupts = <1>;
|
|
|
|
device_type = "pci";
|
|
|
|
resets = <&rst 6>, <&rst 7>;
|
|
reset-names = "hc", "phy";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupt-map-mask = <0 0 0 1>;
|
|
interrupt-map = <0 0 0 0 &pcie0 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wmac: wmac@18100000 {
|
|
compatible = "qca,qca9550-wmac";
|
|
reg = <0x18100000 0x10000>;
|
|
|
|
interrupt-parent = <&intc2>;
|
|
interrupts = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1: pcie-controller@18250000 {
|
|
compatible = "qcom,qca9550-pci", "qcom,ar7240-pci";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
bus-range = <0x0 0x0>;
|
|
reg = <0x18250000 0x1000>, /* CRP */
|
|
<0x18280000 0x100>, /* CTRL */
|
|
<0x16000000 0x1000>; /* CFG */
|
|
reg-names = "crp_base", "ctrl_base", "cfg_base";
|
|
ranges = <0x2000000 0 0x12000000 0x12000000 0 0x02000000 /* pci memory */
|
|
0x1000000 0 0x00000000 0x0000001 0 0x000001>; /* io space */
|
|
interrupt-parent = <&intc3>;
|
|
interrupts = <0>;
|
|
|
|
device_type = "pci";
|
|
|
|
resets = <&rst2 6>, <&rst2 7>;
|
|
reset-names = "hc", "phy";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupt-map-mask = <0 0 0 1>;
|
|
interrupt-map = <0 0 0 0 &pcie1 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb0: usb@1b000000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0x1b000000 0x1fc>;
|
|
|
|
interrupt-parent = <&intc3>;
|
|
interrupts = <1>;
|
|
resets = <&rst 5>;
|
|
reset-names = "usb-host";
|
|
|
|
has-transaction-translator;
|
|
caps-offset = <0x100>;
|
|
|
|
phy-names = "usb-phy0";
|
|
phys = <&usb_phy0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
usb1: usb@1b400000 {
|
|
compatible = "generic-ehci";
|
|
reg = <0x1b400000 0x1fc>;
|
|
|
|
interrupt-parent = <&intc3>;
|
|
interrupts = <2>;
|
|
resets = <&rst2 5>;
|
|
reset-names = "usb-host";
|
|
|
|
has-transaction-translator;
|
|
caps-offset = <0x100>;
|
|
|
|
phy-names = "usb-phy1";
|
|
phys = <&usb_phy1>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
nand: nand@1b800200 {
|
|
compatible = "qca,ar934x-nand";
|
|
reg = <0x1b800200 0xb8>;
|
|
|
|
interrupts = <21>;
|
|
interrupt-parent = <&miscintc>;
|
|
|
|
resets = <&rst 14>;
|
|
reset-names = "nand";
|
|
|
|
nand-ecc-mode = "hw";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi: spi@1f000000 {
|
|
compatible = "qca,ar934x-spi";
|
|
reg = <0x1f000000 0x1c>;
|
|
|
|
clocks = <&pll ATH79_CLK_AHB>;
|
|
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&mdio0 {
|
|
compatible = "qca,ar9340-mdio";
|
|
};
|
|
|
|
ð0 {
|
|
compatible = "qca,qca9550-eth", "syscon";
|
|
|
|
pll-reg = <0 0x28 0>;
|
|
pll-handle = <&pll>;
|
|
|
|
pll-data = <0x16000000 0x00000101 0x00001616>;
|
|
phy-mode = "rgmii";
|
|
|
|
resets = <&rst 9>, <&rst 22>;
|
|
reset-names = "mac", "mdio";
|
|
};
|
|
|
|
&mdio1 {
|
|
compatible = "qca,ar9340-mdio";
|
|
};
|
|
|
|
ð1 {
|
|
compatible = "qca,qca9550-eth", "syscon";
|
|
|
|
pll-reg = <0 0x48 0>;
|
|
pll-handle = <&pll>;
|
|
|
|
pll-data = <0x16000000 0x00000101 0x00001616>;
|
|
phy-mode = "sgmii";
|
|
|
|
resets = <&rst 13>, <&rst 23>;
|
|
reset-names = "mac", "mdio";
|
|
};
|