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The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
50 lines
1.9 KiB
Diff
50 lines
1.9 KiB
Diff
From de6a4aa502318ed5bfbf707b93fb62e786b93bea Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Thu, 16 Nov 2023 14:39:30 +0000
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Subject: [PATCH 0831/1085] vc4/hdmi: Update MAI_THR for D0
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2712D0 has increased the fifo sizes of MAI_THR blocks,
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resulting in adjusted bit offsets. Handle that.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_hdmi.c | 8 +++++++-
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drivers/gpu/drm/vc4/vc4_regs.h | 9 +++++++++
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2 files changed, 16 insertions(+), 1 deletion(-)
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--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
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+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
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@@ -2597,7 +2597,13 @@ static int vc4_hdmi_audio_prepare(struct
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VC4_HDMI_AUDIO_PACKET_CEA_MASK);
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/* Set the MAI threshold */
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- if (vc4->gen >= VC4_GEN_5)
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+ if (vc4->gen >= VC4_GEN_5 && vc4->step_d0)
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+ HDMI_WRITE(HDMI_MAI_THR,
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+ VC4_SET_FIELD(0x10, VC4_D0_HD_MAI_THR_PANICHIGH) |
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+ VC4_SET_FIELD(0x10, VC4_D0_HD_MAI_THR_PANICLOW) |
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+ VC4_SET_FIELD(0x1c, VC4_D0_HD_MAI_THR_DREQHIGH) |
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+ VC4_SET_FIELD(0x1c, VC4_D0_HD_MAI_THR_DREQLOW));
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+ else if (vc4->gen >= VC4_GEN_5)
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HDMI_WRITE(HDMI_MAI_THR,
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VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
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VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -1039,6 +1039,15 @@ enum {
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# define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0)
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# define VC4_HD_MAI_THR_DREQLOW_SHIFT 0
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+# define VC4_D0_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 23)
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+# define VC4_D0_HD_MAI_THR_PANICHIGH_SHIFT 23
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+# define VC4_D0_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 15)
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+# define VC4_D0_HD_MAI_THR_PANICLOW_SHIFT 15
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+# define VC4_D0_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 7)
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+# define VC4_D0_HD_MAI_THR_DREQHIGH_SHIFT 7
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+# define VC4_D0_HD_MAI_THR_DREQLOW_MASK VC4_MASK(6, 0)
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+# define VC4_D0_HD_MAI_THR_DREQLOW_SHIFT 0
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+
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/* Divider from HDMI HSM clock to MAI serial clock. Sampling period
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* converges to N / (M + 1) cycles.
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*/
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