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250 lines
6.2 KiB
Diff
250 lines
6.2 KiB
Diff
From b3b3cd885ed39cb4b38319a1c4fa4e41db6fee72 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
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Date: Mon, 15 May 2023 17:19:20 +0200
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Subject: [PATCH] ARM: dts: BCM5301X: Relicense Hauke's code to the GPL 2.0+ /
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MIT
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Move code added by Hauke to the bcm-ns.dtsi which uses dual licensing.
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That syncs more Northstar code to be based on the same licensing schema.
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Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
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Cc: Hauke Mehrtens <hauke@hauke-m.de>
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Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
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Link: https://lore.kernel.org/r/20230515151921.25021-1-zajec5@gmail.com
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Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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---
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arch/arm/boot/dts/bcm-ns.dtsi | 90 +++++++++++++++++++++++++++++++++
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arch/arm/boot/dts/bcm5301x.dtsi | 85 -------------------------------
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2 files changed, 90 insertions(+), 85 deletions(-)
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--- a/arch/arm/boot/dts/bcm-ns.dtsi
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+++ b/arch/arm/boot/dts/bcm-ns.dtsi
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@@ -1,4 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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+/*
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+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
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+ */
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#include <dt-bindings/clock/bcm-nsp.h>
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#include <dt-bindings/gpio/gpio.h>
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@@ -7,6 +10,81 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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+ interrupt-parent = <&gic>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ chipcommon-a-bus@18000000 {
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+ compatible = "simple-bus";
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+ ranges = <0x00000000 0x18000000 0x00001000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ uart0: serial@300 {
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+ compatible = "ns16550";
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+ reg = <0x0300 0x100>;
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+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&iprocslow>;
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+ status = "disabled";
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+ };
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+
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+ uart1: serial@400 {
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+ compatible = "ns16550";
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+ reg = <0x0400 0x100>;
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+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&iprocslow>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinmux_uart1>;
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+ status = "disabled";
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+ };
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+ };
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+
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+ mpcore-bus@19000000 {
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+ compatible = "simple-bus";
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+ ranges = <0x00000000 0x19000000 0x00023000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ scu@20000 {
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+ compatible = "arm,cortex-a9-scu";
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+ reg = <0x20000 0x100>;
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+ };
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+
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+ timer@20200 {
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+ compatible = "arm,cortex-a9-global-timer";
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+ reg = <0x20200 0x100>;
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+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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+ clocks = <&periph_clk>;
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+ };
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+
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+ timer@20600 {
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+ compatible = "arm,cortex-a9-twd-timer";
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+ reg = <0x20600 0x20>;
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+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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+ IRQ_TYPE_EDGE_RISING)>;
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+ clocks = <&periph_clk>;
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+ };
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+
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+ gic: interrupt-controller@21000 {
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+ compatible = "arm,cortex-a9-gic";
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+ #interrupt-cells = <3>;
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+ #address-cells = <0>;
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+ interrupt-controller;
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+ reg = <0x21000 0x1000>,
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+ <0x20100 0x100>;
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+ };
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+
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+ L2: cache-controller@22000 {
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+ compatible = "arm,pl310-cache";
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+ reg = <0x22000 0x1000>;
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+ cache-unified;
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+ arm,shared-override;
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+ prefetch-data = <1>;
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+ prefetch-instr = <1>;
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+ cache-level = <2>;
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+ };
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+ };
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+
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axi@18000000 {
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compatible = "brcm,bus-axi";
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reg = <0x18000000 0x1000>;
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@@ -216,6 +294,18 @@
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};
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};
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+ nand_controller: nand-controller@18028000 {
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+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
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+ reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
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+ reg-names = "nand", "iproc-idm", "iproc-ext";
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+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ brcm,nand-has-wp;
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+ };
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+
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <0>;
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--- a/arch/arm/boot/dts/bcm5301x.dtsi
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+++ b/arch/arm/boot/dts/bcm5301x.dtsi
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@@ -11,41 +11,7 @@
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#include "bcm-ns.dtsi"
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/ {
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- #address-cells = <1>;
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- #size-cells = <1>;
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- interrupt-parent = <&gic>;
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-
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- chipcommon-a-bus@18000000 {
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- compatible = "simple-bus";
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- ranges = <0x00000000 0x18000000 0x00001000>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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-
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- uart0: serial@300 {
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- compatible = "ns16550";
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- reg = <0x0300 0x100>;
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- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&iprocslow>;
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- status = "disabled";
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- };
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-
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- uart1: serial@400 {
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- compatible = "ns16550";
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- reg = <0x0400 0x100>;
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- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&iprocslow>;
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- pinctrl-names = "default";
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- pinctrl-0 = <&pinmux_uart1>;
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- status = "disabled";
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- };
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- };
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-
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mpcore-bus@19000000 {
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- compatible = "simple-bus";
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- ranges = <0x00000000 0x19000000 0x00023000>;
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- #address-cells = <1>;
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- #size-cells = <1>;
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-
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a9pll: arm_clk@0 {
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#clock-cells = <0>;
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compatible = "brcm,nsp-armpll";
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@@ -53,26 +19,6 @@
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reg = <0x00000 0x1000>;
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};
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- scu@20000 {
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- compatible = "arm,cortex-a9-scu";
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- reg = <0x20000 0x100>;
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- };
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-
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- timer@20200 {
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- compatible = "arm,cortex-a9-global-timer";
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- reg = <0x20200 0x100>;
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- interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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- clocks = <&periph_clk>;
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- };
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-
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- timer@20600 {
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- compatible = "arm,cortex-a9-twd-timer";
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- reg = <0x20600 0x20>;
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- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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- IRQ_TYPE_EDGE_RISING)>;
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- clocks = <&periph_clk>;
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- };
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-
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watchdog@20620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0x20620 0x20>;
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@@ -80,25 +26,6 @@
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IRQ_TYPE_EDGE_RISING)>;
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clocks = <&periph_clk>;
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};
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-
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- gic: interrupt-controller@21000 {
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- compatible = "arm,cortex-a9-gic";
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- #interrupt-cells = <3>;
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- #address-cells = <0>;
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- interrupt-controller;
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- reg = <0x21000 0x1000>,
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- <0x20100 0x100>;
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- };
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-
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- L2: cache-controller@22000 {
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- compatible = "arm,pl310-cache";
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- reg = <0x22000 0x1000>;
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- cache-unified;
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- arm,shared-override;
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- prefetch-data = <1>;
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- prefetch-instr = <1>;
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- cache-level = <2>;
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- };
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};
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pmu {
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@@ -301,18 +228,6 @@
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};
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};
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- nand_controller: nand-controller@18028000 {
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- compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
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- reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
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- reg-names = "nand", "iproc-idm", "iproc-ext";
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- interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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-
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- #address-cells = <1>;
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- #size-cells = <0>;
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-
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- brcm,nand-has-wp;
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- };
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-
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spi@18029200 {
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compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
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reg = <0x18029200 0x184>,
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