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65044a50ab
Refreshed all patches. Removed upstreamed: - 203-MIPS-ath79-fix-restart.patch - 330-Revert-MIPS-BCM47XX-Enable-74K-Core-ExternalSync-for.patch - 051-0001-ovl-rename-is_merge-to-is_lowest.patch - 051-0002-ovl-override-creds-with-the-ones-from-the-superblock.patch - 051-0005-ovl-proper-cleanup-of-workdir.patch Altered patches: - 201-extra_optimization.patch - 304-mips_disable_fpu.patch Compile-tested on: ar71xx, cns3xxx, imx6, mpc85xx Runtime-tested on: ar71xx, cns3xxx, imx6, mpc85xx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
42 lines
1.2 KiB
Diff
42 lines
1.2 KiB
Diff
From e892dea7229d56b75c46a76b9039f9e179584a91 Mon Sep 17 00:00:00 2001
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From: Yunhui Cui <B56489@freescale.com>
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Date: Mon, 1 Feb 2016 18:48:49 +0800
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Subject: [PATCH 100/113] mtd:spi_nor: Disable Micron flash HW protection
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For Micron family ,The status register write enable/disable bit,
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provides hardware data protection for the device.
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When the enable/disable bit is set to 1, the status register
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nonvolatile bits become read-only and the WRITE STATUS REGISTER
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operation will not execute.
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Signed-off-by: Yunhui Cui <B56489@freescale.com>
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---
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drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
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1 file changed, 9 insertions(+)
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -39,6 +39,7 @@
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#define SPI_NOR_MAX_ID_LEN 6
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#define SPI_NOR_MAX_ADDR_WIDTH 4
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+#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
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struct flash_info {
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char *name;
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@@ -1252,6 +1253,14 @@ int spi_nor_scan(struct spi_nor *nor, co
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if (ret)
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return ret;
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+ if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
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+ ret = read_sr(nor);
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+ ret &= SPI_NOR_MICRON_WRITE_ENABLE;
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+
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+ write_enable(nor);
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+ write_sr(nor, ret);
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+ }
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+
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if (!mtd->name)
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mtd->name = dev_name(dev);
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mtd->priv = nor;
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