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Refresh all patches on top of kernel 5.10.138. The following patches were applied upstream: bcm27xx/patches-5.10/950-0311-drm-vc4-Adopt-the-dma-configuration-from-the-HVS-or-.patch bcm27xx/patches-5.10/950-0317-vc4_hdmi-Remove-firmware-logic-for-MAI-threshold-set.patch bcm27xx/patches-5.10/950-0346-drm-vc4-A-present-but-empty-dmas-disables-audio.patch bcm27xx/patches-5.10/950-0354-drm-vc4-Add-the-2711-HVS-as-a-suitable-DMA-node.patch bcm27xx/patches-5.10/950-0413-drm-vc4-hdmi-Don-t-access-the-connector-state-in-res.patch bcm27xx/patches-5.10/950-0505-vc4-drm-Avoid-full-hdmi-audio-fifo-writes.patch bcm27xx/patches-5.10/950-0512-vc4-drm-vc4_plane-Remove-subpixel-positioning-check.patch bcm27xx/patches-5.10/950-0560-drm-vc4-drv-Remove-the-DSI-pointer-in-vc4_drv.patch bcm27xx/patches-5.10/950-0561-drm-vc4-dsi-Use-snprintf-for-the-PHY-clocks-instead-.patch bcm27xx/patches-5.10/950-0562-drm-vc4-dsi-Introduce-a-variant-structure.patch bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch bcm27xx/patches-5.10/950-0566-drm-vc4-Register-dsi0-as-the-correct-vc4-encoder-typ.patch bcm27xx/patches-5.10/950-0567-drm-vc4-Fix-dsi0-interrupt-support.patch bcm27xx/patches-5.10/950-0568-drm-vc4-Add-correct-stop-condition-to-vc4_dsi_encode.patch bcm27xx/patches-5.10/950-0647-drm-vc4-Fix-timings-for-interlaced-modes.patch bcm27xx/patches-5.10/950-0695-drm-vc4-Fix-margin-calculations-for-the-right-bottom.patch Upstream sets the pixel clock to 340MHz now, do not set it to 600MHz any more. bcm27xx/patches-5.10/950-0576-drm-vc4-hdmi-Raise-the-maximum-clock-rate.patch Fixes:89956c6532("kernel: bump 5.10 to 5.10.138") Fixes:4209c33ae2("kernel: bump 5.10 to 5.10.137") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
106 lines
3.8 KiB
Diff
106 lines
3.8 KiB
Diff
From f5c7dd20b383a4ab8212736b37940a4339d80e33 Mon Sep 17 00:00:00 2001
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From: Dom Cobley <popcornmix@gmail.com>
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Date: Mon, 12 Apr 2021 17:27:43 +0100
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Subject: [PATCH] vc4/kms: vc4_plane: Support 2020 colourspace for yuv
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planes
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https://gist.github.com/popcornmix/6b3e23103c60170b02b148e0ba5d6ed7
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is the script used to generate the 601, 709 and 2020 colourspaces.
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I've regenetated the existing ones using script so it is reprocable
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but there are lsb dfferences compared to values here (copied from spec)
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whose origin is now lost.
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Signed-off-by: Dom Cobley <popcornmix@gmail.com>
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---
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drivers/gpu/drm/vc4/vc4_plane.c | 19 ++++++++++---------
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drivers/gpu/drm/vc4/vc4_regs.h | 18 ++++++++++++------
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2 files changed, 22 insertions(+), 15 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_plane.c
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+++ b/drivers/gpu/drm/vc4/vc4_plane.c
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@@ -645,10 +645,10 @@ static const u32 colorspace_coeffs[2][DR
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SCALER_CSC1_ITR_R_709_3,
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SCALER_CSC2_ITR_R_709_3,
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}, {
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- /* BT2020. Not supported yet - copy 601 */
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- SCALER_CSC0_ITR_R_601_5,
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- SCALER_CSC1_ITR_R_601_5,
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- SCALER_CSC2_ITR_R_601_5,
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+ /* BT2020 */
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+ SCALER_CSC0_ITR_R_2020,
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+ SCALER_CSC1_ITR_R_2020,
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+ SCALER_CSC2_ITR_R_2020,
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}
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}, {
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/* Full range */
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@@ -663,10 +663,10 @@ static const u32 colorspace_coeffs[2][DR
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SCALER_CSC1_ITR_R_709_3_FR,
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SCALER_CSC2_ITR_R_709_3_FR,
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}, {
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- /* BT2020. Not supported yet - copy JFIF */
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- SCALER_CSC0_JPEG_JFIF,
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- SCALER_CSC1_JPEG_JFIF,
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- SCALER_CSC2_JPEG_JFIF,
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+ /* BT2020 */
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+ SCALER_CSC0_ITR_R_2020_FR,
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+ SCALER_CSC1_ITR_R_2020_FR,
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+ SCALER_CSC2_ITR_R_2020_FR,
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}
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}
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};
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@@ -1488,7 +1488,8 @@ struct drm_plane *vc4_plane_init(struct
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drm_plane_create_color_properties(plane,
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BIT(DRM_COLOR_YCBCR_BT601) |
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- BIT(DRM_COLOR_YCBCR_BT709),
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+ BIT(DRM_COLOR_YCBCR_BT709) |
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+ BIT(DRM_COLOR_YCBCR_BT2020),
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BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
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BIT(DRM_COLOR_YCBCR_FULL_RANGE),
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DRM_COLOR_YCBCR_BT709,
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--- a/drivers/gpu/drm/vc4/vc4_regs.h
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+++ b/drivers/gpu/drm/vc4/vc4_regs.h
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@@ -975,8 +975,10 @@ enum hvs_pixel_format {
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#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
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#define SCALER_CSC0_ITR_R_601_5 0x00f00000
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#define SCALER_CSC0_ITR_R_709_3 0x00f00000
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+#define SCALER_CSC0_ITR_R_2020 0x00f00000
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#define SCALER_CSC0_JPEG_JFIF 0x00000000
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#define SCALER_CSC0_ITR_R_709_3_FR 0x00000000
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+#define SCALER_CSC0_ITR_R_2020_FR 0x00000000
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/* S2.8 contribution of Cb to Green */
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#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
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@@ -991,9 +993,11 @@ enum hvs_pixel_format {
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#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
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#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
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#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
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-#define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
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-#define SCALER_CSC1_JPEG_JFIF 0xea34a400
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-#define SCALER_CSC1_ITR_R_709_3_FR 0xe23d0400
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+#define SCALER_CSC1_ITR_R_709_3 0xf27784a8
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+#define SCALER_CSC1_ITR_R_2020 0xf43594a8
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+#define SCALER_CSC1_JPEG_JFIF 0xea349400
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+#define SCALER_CSC1_ITR_R_709_3_FR 0xf4388400
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+#define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d400
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/* S2.8 contribution of Cb to Red */
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#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
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@@ -1004,10 +1008,12 @@ enum hvs_pixel_format {
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/* S2.8 contribution of Cb to Blue */
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#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
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#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
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-#define SCALER_CSC2_ITR_R_601_5 0x00066204
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-#define SCALER_CSC2_ITR_R_709_3 0x00072a1c
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-#define SCALER_CSC2_JPEG_JFIF 0x000599c5
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+#define SCALER_CSC2_ITR_R_601_5 0x00066604
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+#define SCALER_CSC2_ITR_R_709_3 0x00072e1d
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+#define SCALER_CSC2_ITR_R_2020 0x0006b624
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+#define SCALER_CSC2_JPEG_JFIF 0x00059dc6
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#define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb
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+#define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e2
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#define SCALER_TPZ0_VERT_RECALC BIT(31)
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#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
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