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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
80 lines
2.4 KiB
Diff
80 lines
2.4 KiB
Diff
From 8c73af6e8d78c66cfef0f551b00d375ec0b67ff3 Mon Sep 17 00:00:00 2001
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From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
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Date: Sat, 30 Jan 2021 10:50:09 +0530
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Subject: [PATCH] remoteproc: qcom: Update regmap offsets for halt register
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Fixed issue in reading halt-regs parameter from device-tree.
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Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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---
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drivers/remoteproc/qcom_q6v5_wcss.c | 22 ++++++++++++++--------
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1 file changed, 14 insertions(+), 8 deletions(-)
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--- a/drivers/remoteproc/qcom_q6v5_wcss.c
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+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
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@@ -86,7 +86,7 @@
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#define TCSR_WCSS_CLK_MASK 0x1F
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#define TCSR_WCSS_CLK_ENABLE 0x14
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-#define MAX_HALT_REG 3
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+#define MAX_HALT_REG 4
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#define WCNSS_PAS_ID 6
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@@ -154,6 +154,7 @@ struct wcss_data {
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u32 version;
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bool aon_reset_required;
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bool wcss_q6_reset_required;
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+ bool bcr_reset_required;
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const char *ssr_name;
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const char *sysmon_name;
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int ssctl_id;
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@@ -875,10 +876,13 @@ static int q6v5_wcss_init_reset(struct q
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}
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}
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- wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_bcr_reset");
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- if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
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- dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
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- return PTR_ERR(wcss->wcss_q6_bcr_reset);
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+ if (desc->bcr_reset_required) {
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+ wcss->wcss_q6_bcr_reset = devm_reset_control_get_exclusive(dev,
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+ "wcss_q6_bcr_reset");
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+ if (IS_ERR(wcss->wcss_q6_bcr_reset)) {
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+ dev_err(wcss->dev, "unable to acquire wcss_q6_bcr_reset\n");
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+ return PTR_ERR(wcss->wcss_q6_bcr_reset);
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+ }
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}
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return 0;
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@@ -929,9 +933,9 @@ static int q6v5_wcss_init_mmio(struct q6
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return -EINVAL;
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}
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- wcss->halt_q6 = halt_reg[0];
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- wcss->halt_wcss = halt_reg[1];
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- wcss->halt_nc = halt_reg[2];
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+ wcss->halt_q6 = halt_reg[1];
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+ wcss->halt_wcss = halt_reg[2];
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+ wcss->halt_nc = halt_reg[3];
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return 0;
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}
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@@ -1178,6 +1182,7 @@ static const struct wcss_data wcss_ipq80
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.crash_reason_smem = WCSS_CRASH_REASON,
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.aon_reset_required = true,
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.wcss_q6_reset_required = true,
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+ .bcr_reset_required = false,
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.ssr_name = "q6wcss",
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.ops = &q6v5_wcss_ipq8074_ops,
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.requires_force_stop = true,
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@@ -1192,6 +1197,7 @@ static const struct wcss_data wcss_qcs40
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.version = WCSS_QCS404,
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.aon_reset_required = false,
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.wcss_q6_reset_required = false,
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+ .bcr_reset_required = true,
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.ssr_name = "mpss",
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.sysmon_name = "wcnss",
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.ssctl_id = 0x12,
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